From patchwork Fri Nov 14 03:59:10 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yinghai Lu X-Patchwork-Id: 410695 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id EDD261400E9 for ; Fri, 14 Nov 2014 14:59:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934063AbaKND7O (ORCPT ); Thu, 13 Nov 2014 22:59:14 -0500 Received: from aserp1040.oracle.com ([141.146.126.69]:33169 "EHLO aserp1040.oracle.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933512AbaKND7O (ORCPT ); Thu, 13 Nov 2014 22:59:14 -0500 Received: from acsinet22.oracle.com (acsinet22.oracle.com [141.146.126.238]) by aserp1040.oracle.com (Sentrion-MTA-4.3.2/Sentrion-MTA-4.3.2) with ESMTP id sAE3x8dv009816 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 14 Nov 2014 03:59:08 GMT Received: from userz7021.oracle.com (userz7021.oracle.com [156.151.31.85]) by acsinet22.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id sAE3x6sX018016 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=FAIL); Fri, 14 Nov 2014 03:59:07 GMT Received: from abhmp0003.oracle.com (abhmp0003.oracle.com [141.146.116.9]) by userz7021.oracle.com (8.14.4+Sun/8.14.4) with ESMTP id sAE3x60X018559; Fri, 14 Nov 2014 03:59:06 GMT Received: from linux-siqj.site (/107.215.0.145) by default (Oracle Beehive Gateway v4.0) with ESMTP ; Thu, 13 Nov 2014 19:59:05 -0800 From: Yinghai Lu To: Bjorn Helgaas , Andrew Morton , "H. Peter Anvin" , Ingo Molnar Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Yinghai Lu Subject: [PATCH] PCI: Don't reject 64bit mmio on 32bit/PAE mode Date: Thu, 13 Nov 2014 19:59:10 -0800 Message-Id: <1415937550-14469-1-git-send-email-yinghai@kernel.org> X-Mailer: git-send-email 1.8.4.5 X-Source-IP: acsinet22.oracle.com [141.146.126.238] Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Aaron reported 32bit/PAE mode, has problem with 64bit resource. [ 6.610012] pci 0000:03:00.0: reg 0x10: [mem 0x383fffc00000-0x383fffdfffff 64bit pref] [ 6.622195] pci 0000:03:00.0: reg 0x20: [mem 0x383fffe04000-0x383fffe07fff 64bit pref] [ 6.656112] pci 0000:03:00.1: reg 0x10: [mem 0x383fffa00000-0x383fffbfffff 64bit pref] [ 6.668293] pci 0000:03:00.1: reg 0x20: [mem 0x383fffe00000-0x383fffe03fff 64bit pref] [ 6.702055] pci 0000:00:02.2: PCI bridge to [bus 03-04] [ 6.706434] pci 0000:00:02.2: bridge window [io 0x1000-0x1fff] [ 6.711783] pci 0000:00:02.2: bridge window [mem 0x91900000-0x91cfffff] [ 6.717906] pci 0000:00:02.2: can't handle 64-bit address space for bridge So the kernel reject 64bit mmio on pci pref bridge that is assigned by firmware. When 32bit PAE is enabled, we could support 64bit mmio. but BITS_PER_LONG==64 checking could reject firmware assigned mmio that is above 4G. On x86 32bit always has BITS_PER_LONG equal to 32. We could use CONFIG_ARCH_DMA_ADDR_T_64BIT or dma_addr_t size checking instead. Use dma_addr_t size checking to avoid using MARCO. Also need to change to use dma_addr_t instead of unsigned long for base/limit to avoid overflow. Link: https://bugzilla.kernel.org/show_bug.cgi?id=88131 Reported-by: Aaron Ma Tested-by: Aaron Ma Signed-off-by: Yinghai Lu --- drivers/pci/probe.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: linux-2.6/drivers/pci/probe.c =================================================================== --- linux-2.6.orig/drivers/pci/probe.c +++ linux-2.6/drivers/pci/probe.c @@ -406,15 +406,15 @@ static void pci_read_bridge_mmio_pref(st { struct pci_dev *dev = child->self; u16 mem_base_lo, mem_limit_lo; - unsigned long base, limit; + dma_addr_t base, limit; struct pci_bus_region region; struct resource *res; res = child->resource[2]; pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); - base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16; - limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; + base = ((dma_addr_t) mem_base_lo & PCI_PREF_RANGE_MASK) << 16; + limit = ((dma_addr_t) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { u32 mem_base_hi, mem_limit_hi; @@ -428,15 +428,15 @@ static void pci_read_bridge_mmio_pref(st * this, just assume they are not being used. */ if (mem_base_hi <= mem_limit_hi) { -#if BITS_PER_LONG == 64 - base |= ((unsigned long) mem_base_hi) << 32; - limit |= ((unsigned long) mem_limit_hi) << 32; -#else - if (mem_base_hi || mem_limit_hi) { - dev_err(&dev->dev, "can't handle 64-bit address space for bridge\n"); - return; + if (sizeof(dma_addr_t) < 8) { + if (mem_base_hi || mem_limit_hi) { + dev_err(&dev->dev, "can't handle 64-bit address space for bridge\n"); + return; + } + } else { + base |= ((dma_addr_t) mem_base_hi) << 32; + limit |= ((dma_addr_t) mem_limit_hi) << 32; } -#endif } } if (base <= limit) {