From patchwork Mon Oct 27 07:48:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yijing Wang X-Patchwork-Id: 403409 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id CB4EC140082 for ; Mon, 27 Oct 2014 18:11:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752664AbaJ0HKk (ORCPT ); Mon, 27 Oct 2014 03:10:40 -0400 Received: from szxga02-in.huawei.com ([119.145.14.65]:10243 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752175AbaJ0HIU (ORCPT ); Mon, 27 Oct 2014 03:08:20 -0400 Received: from 172.24.2.119 (EHLO szxeml409-hub.china.huawei.com) ([172.24.2.119]) by szxrg02-dlp.huawei.com (MOS 4.3.7-GA FastPath queued) with ESMTP id CBJ05358; Mon, 27 Oct 2014 15:07:32 +0800 (CST) Received: from localhost.localdomain (10.175.100.166) by szxeml409-hub.china.huawei.com (10.82.67.136) with Microsoft SMTP Server id 14.3.158.1; Mon, 27 Oct 2014 15:07:24 +0800 From: Yijing Wang To: Bjorn Helgaas CC: , , Xinwei Hu , Wuyun , , Russell King , Thomas Gleixner , "Thierry Reding" , Thomas Petazzoni , Yijing Wang Subject: [PATCH 08/10] PCI: xilinx: Save MSI controller in pci_sys_data Date: Mon, 27 Oct 2014 15:48:45 +0800 Message-ID: <1414396127-30023-9-git-send-email-wangyijing@huawei.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1414396127-30023-1-git-send-email-wangyijing@huawei.com> References: <1414396127-30023-1-git-send-email-wangyijing@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.100.166] X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every pci bus in .add_bus(). Signed-off-by: Yijing Wang --- drivers/pci/host/pcie-xilinx.c | 19 ++++--------------- 1 files changed, 4 insertions(+), 15 deletions(-) diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c index ce19133..5a3e5a0 100644 --- a/drivers/pci/host/pcie-xilinx.c +++ b/drivers/pci/host/pcie-xilinx.c @@ -431,20 +431,6 @@ static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port) pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2); } -/** - * xilinx_pcie_add_bus - Add MSI chip info to PCIe bus - * @bus: PCIe bus - */ -static void xilinx_pcie_add_bus(struct pci_bus *bus) -{ - if (IS_ENABLED(CONFIG_PCI_MSI)) { - struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata); - - xilinx_pcie_msi_controller.dev = port->dev; - bus->msi = &xilinx_pcie_msi_controller; - } -} - /* INTx Functions */ /** @@ -924,10 +910,13 @@ static int xilinx_pcie_probe(struct platform_device *pdev) .private_data = (void **)&port, .setup = xilinx_pcie_setup, .map_irq = of_irq_parse_and_map_pci, - .add_bus = xilinx_pcie_add_bus, .scan = xilinx_pcie_scan_bus, .ops = &xilinx_pcie_ops, }; +#ifdef CONFIG_PCI_MSI + xilinx_pcie_msi_controller.dev = port->dev; + hw.msi_ctrl = &xilinx_pcie_msi_controller; +#endif pci_common_init_dev(dev, &hw); return 0;