From patchwork Wed Sep 24 15:37:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Richter X-Patchwork-Id: 393004 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C2986140174 for ; Thu, 25 Sep 2014 01:38:59 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752738AbaIXPiI (ORCPT ); Wed, 24 Sep 2014 11:38:08 -0400 Received: from mail-wg0-f52.google.com ([74.125.82.52]:33536 "EHLO mail-wg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753119AbaIXPiG (ORCPT ); Wed, 24 Sep 2014 11:38:06 -0400 Received: by mail-wg0-f52.google.com with SMTP id n12so4673783wgh.23 for ; Wed, 24 Sep 2014 08:38:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=SspyGIrcLYYvgKwHR77PJKHnmPh6SYf2Ph4N+QyUzCE=; b=t/RiNi7nC6xIHI0BRwNl3HQLhIjDD4v/GoFUJ5R62Tpo/SOxznfmqPjY/WEI6yGw/x 23QjSts+egba2dLL8WhLYggFozga/WNEvEYaoY3QGRv5e8F00177sg/hhx2juvqufnWF jhzrwbu6XW4HIY8bpIAJ5W/kSGM2vBO6eJFOgz438NcWuJrzgWEcsQjZa/0AkBN8qz05 7IbeKrvgOdcNIs+2aCIEGRfcVwPMOlsUtxgpytX8dRDPZ5XIUG509+c0tOWmvCBMMV59 rnPhIfkmN55AwEZlBMwPBxBkOuVrkQbUiY/IccgSls0+LE2K/fZ0JOkwlKwitXH+1VHK 5r3g== X-Received: by 10.180.101.202 with SMTP id fi10mr12451851wib.17.1411573085415; Wed, 24 Sep 2014 08:38:05 -0700 (PDT) Received: from rric.localhost (f053087200.adsl.alicedsl.de. [78.53.87.200]) by mx.google.com with ESMTPSA id ky3sm19788016wjb.39.2014.09.24.08.38.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 24 Sep 2014 08:38:04 -0700 (PDT) From: Robert Richter To: Bjorn Helgaas , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon Cc: Liviu Dudau , Arnd Bergmann , Sunil Goutham , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Robert Richter , devicetree@vger.kernel.org Subject: [PATCH 3/6] pci, thunder: Add PCIe host controller devicetree bindings Date: Wed, 24 Sep 2014 17:37:45 +0200 Message-Id: <1411573068-12952-4-git-send-email-rric@kernel.org> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1411573068-12952-1-git-send-email-rric@kernel.org> References: <1411573068-12952-1-git-send-email-rric@kernel.org> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Sunil Goutham This patch adds the PCIe host controller entry for Cavium Thunder SoCs to the devicetree. There are 4 internal PCI controllers available. Signed-off-by: Sunil Goutham Signed-off-by: Robert Richter --- arch/arm64/boot/dts/thunder-88xx.dtsi | 49 +++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/thunder-88xx.dtsi b/arch/arm64/boot/dts/thunder-88xx.dtsi index 9cb7cf94284a..0b433b0e7af4 100644 --- a/arch/arm64/boot/dts/thunder-88xx.dtsi +++ b/arch/arm64/boot/dts/thunder-88xx.dtsi @@ -407,4 +407,53 @@ clock-names = "apb_pclk"; }; }; + + pcie0@0x8480,00000000 { + compatible = "cavium,thunder-pcie"; + device_type = "pci"; + msi-parent = <&its>; + bus-range = <0 255>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ + ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>, /* mem ranges */ + <0x03000000 0x8300 0x00000000 0x8300 0x00000000 0x80 0x00000000>, + <0x03000000 0x87e0 0x00000000 0x87e0 0x00000000 0x01 0x00000000>; + }; + + pcie1@0x8490,00000000 { + compatible = "cavium,thunder-pcie"; + device_type = "pci"; + msi-parent = <&its>; + bus-range = <0 255>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x8490 0x00000000 0 0x10000000>; /* Configuration space */ + ranges = <0x03000000 0x8310 0x00000000 0x8310 0x00000000 0x00 0x10000000>, /* mem ranges */ + <0x03000000 0x8100 0x00000000 0x8100 0x00000000 0x80 0x00000000>; + }; + + pcie2@0x84a0,00000000 { + compatible = "cavium,thunder-pcie"; + device_type = "pci"; + msi-parent = <&its>; + bus-range = <0 255>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x84a0 0x00000000 0 0x10000000>; /* Configuration space */ + ranges = <0x03000000 0x8320 0x00000000 0x8320 0x00000000 0x00 0x10000000>, /* mem ranges */ + <0x03000000 0x8430 0x00000000 0x8430 0x00000000 0x01 0x00000000>; + }; + + pcie3@0x84b0,00000000 { + compatible = "cavium,thunder-pcie"; + device_type = "pci"; + msi-parent = <&its>; + bus-range = <0 255>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x84b0 0x00000000 0 0x10000000>; /* Configuration space */ + ranges = <0x03000000 0x8330 0x00000000 0x8330 0x00000000 0x00 0x10000000>, /* mem ranges */ + <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; + }; };