From patchwork Wed Sep 3 04:04:37 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 385384 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 61D0E1401F5 for ; Wed, 3 Sep 2014 14:05:32 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751004AbaICEFb (ORCPT ); Wed, 3 Sep 2014 00:05:31 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:41897 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750723AbaICEFa (ORCPT ); Wed, 3 Sep 2014 00:05:30 -0400 Received: by mail-pa0-f42.google.com with SMTP id lf10so16375323pab.1 for ; Tue, 02 Sep 2014 21:05:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=H51aJYL5kRfep+qoD7mY/i8YkSQKNZZVVawo/DchP+A=; b=lQ3mcelVKPN150ctdgIRu+10YLeWer2E+WIRI+UWZqRUQntINH2YEDsuKsu5U6zdm2 8vuQUQ4lD9ENLiO70bkuvuOSCVd4PPFsMfaZ6C52jjUz2KLrsrr5zRe9iK8COiVB6hqi V3fCvPUQOwviZUd9JHF3lPPhZ6vwHZp54BGRGrb5WZ2WxuSDkaE2m9OHdjrrJM2lT/0g HOyD5aGMolfcnLlfUxCmzrS/8u/8r9pAj2+hEkiffc66BjjEWbd0BfuG/oI+4y9SRBYQ 5dMBV/mgVHZl083ZhWtZcSDMx1Yq660wk5NYFrHZma1ZhlTmSu34/uCFiCN3y06NV+/R eU6w== X-Gm-Message-State: ALoCoQkg1wkZFxF8v5xhc2QP4NClQAgxp32RBILB57YN3obqDJXT2Cn7oMWwSNp5vOwkgkH1Vf4Q X-Received: by 10.66.222.97 with SMTP id ql1mr25376445pac.119.1409717127108; Tue, 02 Sep 2014 21:05:27 -0700 (PDT) Received: from tharvey-gw.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id ef4sm16038758pac.2.2014.09.02.21.05.26 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 02 Sep 2014 21:05:26 -0700 (PDT) From: Tim Harvey To: l.stach@pengutronix.de Cc: Fabio Estevam , shawn.guo@freescale.com, marex@denx.de, bhelgaas@google.com, linux-pci@vger.kernel.org Subject: [PATCH] PCI: imx6: fix occasional link failure Date: Tue, 2 Sep 2014 21:04:37 -0700 Message-Id: <1409717077-26662-1-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: References: Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey Tested-by: Fabio Estevam Acked-by: Marek Vasut Acked-by: Lucas Stach --- v2: - added Tested-by Fabio Estevam - added Acked-by Marek Vasut --- drivers/pci/host/pci-imx6.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 1be6073..9b6bab9 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -256,11 +256,6 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); int ret; - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); - ret = clk_prepare_enable(imx6_pcie->pcie_phy); if (ret) { dev_err(pp->dev, "unable to enable pcie_phy clock\n"); @@ -282,6 +277,12 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) /* allow the clocks to stabilize */ usleep_range(200, 500); + /* power up core phy and enable ref clock */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0);