From patchwork Mon Mar 31 10:30:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Phil Edworthy X-Patchwork-Id: 335253 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4D7201400B2 for ; Mon, 31 Mar 2014 21:31:09 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753938AbaCaKbG (ORCPT ); Mon, 31 Mar 2014 06:31:06 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:31759 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753819AbaCaKbF (ORCPT ); Mon, 31 Mar 2014 06:31:05 -0400 Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie1.idc.renesas.com with ESMTP; 31 Mar 2014 19:31:03 +0900 Received: from relmlac2.idc.renesas.com (relmlac2.idc.renesas.com [10.200.69.22]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id CE86C49BFC; Mon, 31 Mar 2014 19:31:03 +0900 (JST) Received: by relmlac2.idc.renesas.com (Postfix, from userid 0) id C0FEE280A5; Mon, 31 Mar 2014 19:31:03 +0900 (JST) Received: from relmlac2.idc.renesas.com (localhost [127.0.0.1]) by relmlac2.idc.renesas.com (Postfix) with ESMTP id B65C3280A7; Mon, 31 Mar 2014 19:31:03 +0900 (JST) Received: from relmlii1.idc.renesas.com [10.200.68.65] by relmlac2.idc.renesas.com with ESMTP id VAD01512; Mon, 31 Mar 2014 19:31:03 +0900 X-IronPort-AV: E=Sophos;i="4.97,764,1389711600"; d="scan'208";a="156682357" Received: from unknown (HELO relay41.aps.necel.com) ([10.29.19.9]) by relmlii1.idc.renesas.com with ESMTP; 31 Mar 2014 19:31:03 +0900 Received: from DU0NOTES13.ad.ree.renesas.com ([172.29.24.131]) by relay41.aps.necel.com (8.14.4+Sun/8.14.4) with ESMTP id s2VAUxF8028292; Mon, 31 Mar 2014 19:31:02 +0900 (JST) Received: from duacsls.ad.ree.renesas.com ([172.29.43.47]) by DU0NOTES13.ad.ree.renesas.com (Lotus Domino Release 8.5.3 HF466) with ESMTP id 2014033112305899-214558 ; Mon, 31 Mar 2014 12:30:58 +0200 From: Phil Edworthy To: linux-pci@vger.kernel.org Cc: linux-sh@vger.kernel.org, LAKML , Bjorn Helgaas , Valentine Barshak , Simon Horman , Magnus Damm , Ben Dooks , Phil Edworthy X-Mailer: git-send-email 1.9.0 In-Reply-To: <1396261856-22465-1-git-send-email-phil.edworthy@renesas.com> References: <1396261856-22465-1-git-send-email-phil.edworthy@renesas.com> X-TNEFEvaluated: 1 Message-ID: <1396261856-22465-4-git-send-email-phil.edworthy@renesas.com> Date: Mon, 31 Mar 2014 11:30:48 +0100 Subject: [PATCH v7 03/10] ARM: shmobile: r8a7790: Add PCIe clock device tree nodes X-MIMETrack: Itemize by SMTP Server on DU0NOTES13/SERVER/REE(Release 8.5.3 HF466|March 09, 2012) at 31.03.2014 12:30:59, Serialize by Router on DU0NOTES13/SERVER/REE(Release 8.5.3 HF466|March 09, 2012) at 31.03.2014 12:31:02, Serialize complete at 31.03.2014 12:31:02 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This patch adds the device tree clock nodes for PCIe Signed-off-by: Phil Edworthy --- arch/arm/boot/dts/r8a7790.dtsi | 7 ++++--- include/dt-bindings/clock/r8a7790-clock.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index da69afc..df9ec61 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -704,16 +704,17 @@ reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, - <&mmc0_clk>, <&rclk_clk>; + <&mmc0_clk>, <&rclk_clk>, <&mp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 - R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 + R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 R8A7790_CLK_PCIE >; clock-output-names = "tpu0", "mmcif1", "sdhi3", "sdhi2", - "sdhi1", "sdhi0", "mmcif0", "cmt1"; + "sdhi1", "sdhi0", "mmcif0", "cmt1", + "pcie"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 6548a5f..840dbc8 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -57,6 +57,7 @@ #define R8A7790_CLK_SDHI1 13 #define R8A7790_CLK_SDHI0 14 #define R8A7790_CLK_MMCIF0 15 +#define R8A7790_CLK_PCIE 19 #define R8A7790_CLK_SSUSB 28 #define R8A7790_CLK_CMT1 29 #define R8A7790_CLK_USBDMAC0 30