From patchwork Mon Oct 29 14:40:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Abbott X-Patchwork-Id: 195016 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A9FB92C008C for ; Tue, 30 Oct 2012 01:40:34 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759269Ab2J2Okd (ORCPT ); Mon, 29 Oct 2012 10:40:33 -0400 Received: from mail.mev.co.uk ([62.49.15.74]:49723 "EHLO mail.mev.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759270Ab2J2Okc (ORCPT ); Mon, 29 Oct 2012 10:40:32 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.mev.co.uk (Postfix) with ESMTP id 1D2DE74147; Mon, 29 Oct 2012 14:40:30 +0000 (GMT) X-Virus-Scanned: Debian amavisd-new at mail.mev.co.uk Received: from mail.mev.co.uk ([127.0.0.1]) by localhost (mantis.mev.local [127.0.0.1]) (amavisd-new, port 10024) with LMTP id pxPGGirwkL79; Mon, 29 Oct 2012 14:40:27 +0000 (GMT) Received: from gentoo-ija64.mev.local (mev-xp64-ian.mev.local [10.0.0.210]) (Authenticated sender: abbotti) by mail.mev.co.uk (Postfix) with ESMTPSA id 886F474022; Mon, 29 Oct 2012 14:40:27 +0000 (GMT) From: Ian Abbott To: linux-pci@vger.kernel.org Cc: Bjorn Helgaas , Ian Abbott Subject: [PATCH 2/2] PCI: add PLX PCI 9050 workaround for some Meilhaus DAQ cards Date: Mon, 29 Oct 2012 14:40:18 +0000 Message-Id: <1351521618-6818-2-git-send-email-abbotti@mev.co.uk> X-Mailer: git-send-email 1.7.12.4 In-Reply-To: <1351521618-6818-1-git-send-email-abbotti@mev.co.uk> References: <1351521618-6818-1-git-send-email-abbotti@mev.co.uk> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Meilhaus ME-2000i and ME-2600i data acquisition cards supported by the Comedi "me_daq" driver use the PLX PCI 9050 PCI Target bridge chip affected by the bug that prevents the chip's local configuration registers being read from BAR0 or BAR1 base addresses that are an odd multiple of 128 bytes. Use the PLX PCI 9050 quirk handler for these devices to re-allocate affected regions to a 256-byte boundary. Signed-off-by: Ian Abbott --- drivers/pci/quirks.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 7e6be56..f9a1b33 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -1814,6 +1814,17 @@ static void __devinit quirk_plx_pci9050(struct pci_dev *dev) } DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, quirk_plx_pci9050); +/* + * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) + * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, + * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, + * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. + * + * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" + * driver. + */ +DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); +DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); static void __devinit quirk_netmos(struct pci_dev *dev) {