From patchwork Tue Jul 24 16:31:34 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 172935 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D46832C0081 for ; Wed, 25 Jul 2012 02:37:38 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932173Ab2GXQg4 (ORCPT ); Tue, 24 Jul 2012 12:36:56 -0400 Received: from mail-yw0-f46.google.com ([209.85.213.46]:51691 "EHLO mail-yw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932172Ab2GXQgz (ORCPT ); Tue, 24 Jul 2012 12:36:55 -0400 Received: by yhmm54 with SMTP id m54so6854967yhm.19 for ; Tue, 24 Jul 2012 09:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=Y/X/Ym5cQl85KvehSsJzA/rwu2m7AFX66SnyTISk21w=; b=XNTskTf9NumMD6q4R0PZhPexpms2m9Up3u2r2cwid6yNywQ/F1kYh7elzwDq6HiQJ6 f3iiCAhRChvr+pjdIUDAWeoTNfrzVqAdqXcG+1QooZ2L5z/4hGiR+OqwIZNuQ5FUwTyW VpjKc6TtmoFS9meAqxJRl0WAPp8/WGXnfZhiELJ+ZfbFNv20wdLQJlpM5+dfKUJcusj4 IvuY1tTN2i3jfmwtKUmGfTPsNKEErGBZuATXmShOiXn/+Cqb1y6fR3b4hQtQ+M/I36KS fHVuZO4Oj3Fb4Qj2/WjRjPBez5iPaC3IRHo/eHYNtEABaFNXhtT0ol6QyAfT/4jpAOJa eLTg== Received: by 10.66.75.229 with SMTP id f5mr5903448paw.47.1343147814267; Tue, 24 Jul 2012 09:36:54 -0700 (PDT) Received: from localhost.localdomain ([221.221.26.244]) by mx.google.com with ESMTPS id wi6sm12457583pbc.35.2012.07.24.09.36.44 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jul 2012 09:36:52 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [RFC PATCH v2 22/32] PCI/chelsio: use PCIe capabilities access functions to simplify implementation Date: Wed, 25 Jul 2012 00:31:34 +0800 Message-Id: <1343147504-25891-23-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343147504-25891-1-git-send-email-jiang.liu@huawei.com> References: <1343147504-25891-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify chelsio ethernet drivers' implementation. Signed-off-by: Jiang Liu --- drivers/net/ethernet/chelsio/cxgb3/t3_hw.c | 19 +++++++------------ drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 10 +++------- drivers/net/ethernet/chelsio/cxgb4/t4_hw.c | 7 +++---- 3 files changed, 13 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c index 44ac2f4..8fadbb3 100644 --- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c @@ -3289,22 +3289,18 @@ static void config_pcie(struct adapter *adap) unsigned int log2_width, pldsize; unsigned int fst_trn_rx, fst_trn_tx, acklat, rpllmt; - pci_read_config_word(adap->pdev, - adap->pdev->pcie_cap + PCI_EXP_DEVCTL, - &val); + pci_pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL, &val); pldsize = (val & PCI_EXP_DEVCTL_PAYLOAD) >> 5; pci_read_config_word(adap->pdev, 0x2, &devid); if (devid == 0x37) { - pci_write_config_word(adap->pdev, - adap->pdev->pcie_cap + PCI_EXP_DEVCTL, + pci_pcie_capability_write_word(adap->pdev, PCI_EXP_DEVCTL, val & ~PCI_EXP_DEVCTL_READRQ & ~PCI_EXP_DEVCTL_PAYLOAD); pldsize = 0; } - pci_read_config_word(adap->pdev, adap->pdev->pcie_cap + PCI_EXP_LNKCTL, - &val); + pci_pcie_capability_read_word(adap->pdev, PCI_EXP_LNKCTL, &val); fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0)); fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx : @@ -3425,15 +3421,14 @@ out_err: static void get_pci_mode(struct adapter *adapter, struct pci_params *p) { static unsigned short speed_map[] = { 33, 66, 100, 133 }; - u32 pci_mode, pcie_cap; + u32 pci_mode; - pcie_cap = pci_pcie_cap(adapter->pdev); - if (pcie_cap) { + if (pci_is_pcie(adapter->pdev)) { u16 val; p->variant = PCI_VARIANT_PCIE; - pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, - &val); + pci_pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, + &val); p->width = (val >> 4) & 0x3f; return; } diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c index e1f96fb..074d3ea 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c @@ -3695,14 +3695,10 @@ static void __devinit print_port_info(const struct net_device *dev) static void __devinit enable_pcie_relaxed_ordering(struct pci_dev *dev) { u16 v; - int pos; - pos = pci_pcie_cap(dev); - if (pos > 0) { - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &v); - v |= PCI_EXP_DEVCTL_RELAX_EN; - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, v); - } + pci_pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); + v |= PCI_EXP_DEVCTL_RELAX_EN; + pci_pcie_capability_write_word(dev, PCI_EXP_DEVCTL, v); } /* diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c index 32e1dd5..e5184e7 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c @@ -2741,11 +2741,10 @@ static void __devinit get_pci_mode(struct adapter *adapter, struct pci_params *p) { u16 val; - u32 pcie_cap = pci_pcie_cap(adapter->pdev); - if (pcie_cap) { - pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, - &val); + if (pci_is_pcie(adapter->pdev)) { + pci_pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, + &val); p->speed = val & PCI_EXP_LNKSTA_CLS; p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; }