From patchwork Tue Jul 24 16:31:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiang Liu X-Patchwork-Id: 172945 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C230D2C0080 for ; Wed, 25 Jul 2012 02:38:43 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755951Ab2GXQfB (ORCPT ); Tue, 24 Jul 2012 12:35:01 -0400 Received: from mail-yw0-f46.google.com ([209.85.213.46]:44927 "EHLO mail-yw0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755930Ab2GXQe7 (ORCPT ); Tue, 24 Jul 2012 12:34:59 -0400 Received: by yhmm54 with SMTP id m54so6852675yhm.19 for ; Tue, 24 Jul 2012 09:34:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=qdu8sFjv8tDoVxFUa/bpQ5v9cTQi9vFZE7WbOgqIrw0=; b=Oymae8EqcD93bCHaz1ffSdmKQzBgujgIyr9M9U1a2wZ4owqmYz06fbw+JeB0H/H0Mr p7DaC7xpxNrjrKg9LH0nk+KZlMTZzl5HegSWawk2AJbLhr6bXJiRt9WY08bFJaluUrar abZTqVejtdTUEnLOCn0p1UzqJe4+ROLi7oiizEQ8g5o//LUZ0rV3WtSB3xapPP1PCLcZ u9KjJ3FRv7I3GGkrLW2pL1n3gcXTE45JHyH29ltMLXvlvzr03yMYrF7M0n37zYSBLEiA kksW3AjxISwBEoSracsWSU9bLFHGzzqGcsRZkX9TyDPoo8U+mngQ0rybtyHtB8GpczlO usNg== Received: by 10.66.77.71 with SMTP id q7mr5907732paw.0.1343147698060; Tue, 24 Jul 2012 09:34:58 -0700 (PDT) Received: from localhost.localdomain ([221.221.26.244]) by mx.google.com with ESMTPS id wi6sm12457583pbc.35.2012.07.24.09.34.47 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jul 2012 09:34:55 -0700 (PDT) From: Jiang Liu To: Bjorn Helgaas , Don Dutile Cc: Jiang Liu , Yinghai Lu , Taku Izumi , "Rafael J . Wysocki" , Kenji Kaneshige , Yijing Wang , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Jiang Liu Subject: [RFC PATCH v2 10/32] PCI/AER: use PCIe capabilities access functions to simplify implementation Date: Wed, 25 Jul 2012 00:31:22 +0800 Message-Id: <1343147504-25891-11-git-send-email-jiang.liu@huawei.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1343147504-25891-1-git-send-email-jiang.liu@huawei.com> References: <1343147504-25891-1-git-send-email-jiang.liu@huawei.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Jiang Liu Use PCIe capabilities access functions to simplify PCIe AER implementation. Signed-off-by: Jiang Liu Signed-off-by: Yijing Wang --- drivers/pci/pcie/aer/aerdrv.c | 16 +++++++--------- drivers/pci/pcie/aer/aerdrv_core.c | 25 ++++++++++--------------- 2 files changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c index f7c6245..cadee93 100644 --- a/drivers/pci/pcie/aer/aerdrv.c +++ b/drivers/pci/pcie/aer/aerdrv.c @@ -122,19 +122,18 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev, static void aer_enable_rootport(struct aer_rpc *rpc) { struct pci_dev *pdev = rpc->rpd->port; - int pos, aer_pos; + int aer_pos; u16 reg16; u32 reg32; - pos = pci_pcie_cap(pdev); /* Clear PCIe Capability's Device Status */ - pci_read_config_word(pdev, pos+PCI_EXP_DEVSTA, ®16); - pci_write_config_word(pdev, pos+PCI_EXP_DEVSTA, reg16); + pci_pcie_capability_read_word(pdev, PCI_EXP_DEVSTA, ®16); + pci_pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, reg16); /* Disable system error generation in response to error messages */ - pci_read_config_word(pdev, pos + PCI_EXP_RTCTL, ®16); + pci_pcie_capability_read_word(pdev, PCI_EXP_RTCTL, ®16); reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK); - pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16); + pci_pcie_capability_write_word(pdev, PCI_EXP_RTCTL, reg16); aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); /* Clear error status */ @@ -396,9 +395,8 @@ static void aer_error_resume(struct pci_dev *dev) u16 reg16; /* Clean up Root device status */ - pos = pci_pcie_cap(dev); - pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, ®16); - pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16); + pci_pcie_capability_read_word(dev, PCI_EXP_DEVSTA, ®16); + pci_pcie_capability_write_word(dev, PCI_EXP_DEVSTA, reg16); /* Clean AER Root Error Status */ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index f551534..a37e277 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c @@ -35,25 +35,22 @@ module_param(nosourceid, bool, 0); int pci_enable_pcie_error_reporting(struct pci_dev *dev) { u16 reg16 = 0; - int pos; if (pcie_aer_get_firmware_first(dev)) return -EIO; - pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); - if (!pos) + if (!pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR)) return -EIO; - pos = pci_pcie_cap(dev); - if (!pos) + if (!pci_is_pcie(dev)) return -EIO; - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16); + pci_pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); reg16 |= (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16); + pci_pcie_capability_write_word(dev, PCI_EXP_DEVCTL, reg16); return 0; } @@ -62,21 +59,19 @@ EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); int pci_disable_pcie_error_reporting(struct pci_dev *dev) { u16 reg16 = 0; - int pos; if (pcie_aer_get_firmware_first(dev)) return -EIO; - pos = pci_pcie_cap(dev); - if (!pos) + if (!pci_is_pcie(dev)) return -EIO; - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16); + pci_pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); reg16 &= ~(PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); - pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, reg16); + pci_pcie_capability_write_word(dev, PCI_EXP_DEVCTL, reg16); return 0; } @@ -151,18 +146,18 @@ static bool is_error_source(struct pci_dev *dev, struct aer_err_info *e_info) */ if (atomic_read(&dev->enable_cnt) == 0) return false; - pos = pci_pcie_cap(dev); - if (!pos) + if (!pci_is_pcie(dev)) return false; /* Check if AER is enabled */ - pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, ®16); + pci_pcie_capability_read_word(dev, PCI_EXP_DEVCTL, ®16); if (!(reg16 & ( PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE))) return false; + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); if (!pos) return false;