From patchwork Mon Jul 16 03:31:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shengzhou Liu X-Patchwork-Id: 171128 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5E1432C028C for ; Mon, 16 Jul 2012 13:53:27 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751136Ab2GPDxW (ORCPT ); Sun, 15 Jul 2012 23:53:22 -0400 Received: from ch1ehsobe003.messaging.microsoft.com ([216.32.181.183]:35533 "EHLO ch1outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751087Ab2GPDxN (ORCPT ); Sun, 15 Jul 2012 23:53:13 -0400 Received: from mail211-ch1-R.bigfish.com (10.43.68.240) by CH1EHSOBE010.bigfish.com (10.43.70.60) with Microsoft SMTP Server id 14.1.225.23; Mon, 16 Jul 2012 03:53:13 +0000 Received: from mail211-ch1 (localhost [127.0.0.1]) by mail211-ch1-R.bigfish.com (Postfix) with ESMTP id EEE9B2204FA; Mon, 16 Jul 2012 03:53:12 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839he5bhf0ah107ah) Received: from mail211-ch1 (localhost.localdomain [127.0.0.1]) by mail211-ch1 (MessageSwitch) id 1342410790684442_24190; Mon, 16 Jul 2012 03:53:10 +0000 (UTC) Received: from CH1EHSMHS002.bigfish.com (snatpool1.int.messaging.microsoft.com [10.43.68.251]) by mail211-ch1.bigfish.com (Postfix) with ESMTP id A4BB82E003F; Mon, 16 Jul 2012 03:53:10 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CH1EHSMHS002.bigfish.com (10.43.70.2) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 16 Jul 2012 03:53:11 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-003.039d.mgd.msft.net (10.84.1.16) with Microsoft SMTP Server (TLS) id 14.2.298.5; Sun, 15 Jul 2012 22:53:10 -0500 Received: from localhost.localdomain (rock.ap.freescale.net [10.193.20.106]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q6G3qvSW007880; Sun, 15 Jul 2012 20:53:07 -0700 From: Shengzhou Liu To: , CC: , Shengzhou Liu Subject: [PATCH 2/2 v2] powerpc/fsl: PCI: add quirk_enable_non_msi_intx_interrupt Date: Mon, 16 Jul 2012 11:31:27 +0800 Message-ID: <1342409487-28256-2-git-send-email-Shengzhou.Liu@freescale.com> X-Mailer: git-send-email 1.6.4 In-Reply-To: <1342409487-28256-1-git-send-email-Shengzhou.Liu@freescale.com> References: <1342409487-28256-1-git-send-email-Shengzhou.Liu@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On current fsl powerpc platforms, the PCIe root port doesn't support generating MSI/MSI-X and INTx interrupt in RC mode (those interrupts are supported only in EP mode). So we use the shared error interrupt by flag PCI_DEV_FLAGS_USE_NON_MSI_INTX_IRQ for PCIe port driver to support AER, Hot-plug etc, services. Signed-off-by: Shengzhou Liu --- v2: separated platform-specific part to arch/powerpc/sysdev. arch/powerpc/sysdev/fsl_pci.c | 2 ++ arch/powerpc/sysdev/fsl_pci.h | 1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 6073288..fb8862f 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -498,6 +498,8 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary) #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, + quirk_enable_non_msi_intx_interrupt); #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) struct mpc83xx_pcie_priv { diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index a39ed5c..a98c6d8 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -91,6 +91,7 @@ struct ccsr_pci { extern int fsl_add_bridge(struct device_node *dev, int is_primary); extern void fsl_pcibios_fixup_bus(struct pci_bus *bus); extern int mpc83xx_add_bridge(struct device_node *dev); +extern void __devinit quirk_enable_non_msi_intx_interrupt(struct pci_dev *dev); u64 fsl_pci_immrbar_base(struct pci_controller *hose); #endif /* __POWERPC_FSL_PCI_H */