From patchwork Fri Jun 21 03:24:26 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 253127 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D790D2C02A7 for ; Fri, 21 Jun 2013 13:24:43 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1030425Ab3FUDYa (ORCPT ); Thu, 20 Jun 2013 23:24:30 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:52216 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030247Ab3FUDY2 (ORCPT ); Thu, 20 Jun 2013 23:24:28 -0400 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MOQ00A3K44GFBI0@mailout2.samsung.com>; Fri, 21 Jun 2013 12:24:27 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.51]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id 0D.E7.11618.A67C3C15; Fri, 21 Jun 2013 12:24:26 +0900 (KST) X-AuditID: cbfee691-b7fef6d000002d62-91-51c3c76a8070 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id D2.BD.28381.A67C3C15; Fri, 21 Jun 2013 12:24:26 +0900 (KST) Received: from DOJG1HAN03 ([12.23.120.99]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MOQ002V144QWXV0@mmp2.samsung.com>; Fri, 21 Jun 2013 12:24:26 +0900 (KST) From: Jingoo Han To: 'Kukjin Kim' , 'Bjorn Helgaas' Cc: linux-samsung-soc@vger.kernel.org, linux-pci@vger.kernel.org, devicetree-discuss@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 'Grant Likely' , 'Andrew Murray' , 'Thomas Petazzoni' , 'Thierry Reding' , 'Jason Gunthorpe' , 'Arnd Bergmann' , 'Surendranath Gurivireddy Balla' , 'Siva Reddy Kallam' , 'Thomas Abraham' , 'Tomasz Figa' , 'Pratyush Anand' , 'Mohit KUMAR' , Jingoo Han Subject: [PATCH V9 3/4] ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC Date: Fri, 21 Jun 2013 12:24:26 +0900 Message-id: <002301ce6e2e$d4fd8ae0$7ef8a0a0$@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Outlook 14.0 Thread-index: Ac5uLtB/wueZ67I3TJy+sAyVxnOwXw== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrAKsWRmVeSWpSXmKPExsVy+t8zY92s44cDDQ5vUrRo/r+d1eLvpGPs FkuaMixeHtK0ODD7IavFqzMb2SwuL7zEavH9hqlF74KrbBabHl9jtbi8aw6bxdl5x9ksZpzf x2SxceovRov2S8oWK5q2Mlosvric2WL9jNcsFrtXLmGxODZjCaPF0wdNTA6iHmvmrWH0+P1r EqNH35SrbB5PNl1k9FiwqdTjzrU9bB6bl9R7nJ+xkNHj+45eoIItqxg9fr7U8Xj6Yy+zx+dN cgG8UVw2Kak5mWWpRfp2CVwZN0/3sRTc56941J3ewLiHp4uRk0NCwERi75YmNghbTOLCvfVA NheHkMAyRonHz+YywRT9vH+NHSIxnVFi1o33jBDOL0aJuVcusYBUsQmoSXz5cpgdxBYR8Je4 drWVBaSIWaCDTWLTvE2sIAlhgXCJqdu/AHVzcLAIqEo0TbIFCfMKWEpcvfCRHcIWlPgx+R7Y TGYBLYn1O48zQdjyEpvXvGWGuEhBYsfZ14wQu/Qkfn/4zgpRIyKx78U7RoiaFxwSPZ0qIDaL gIDEt8mHWEDWSgjISmw6ADVGUuLgihssExjFZiHZPAvJ5llINs9CsmEBI8sqRtHUguSC4qT0 IlO94sTc4tK8dL3k/NxNjJDUMnEH4/0D1ocYk4HWT2SWEk3OB6amvJJ4Q2MzIwtTE1NjI3NL M9KElcR51VusA4UE0hNLUrNTUwtSi+KLSnNSiw8xMnFwSjUw9hbNsO5riPz+8erV11m3NR1z DJZEneyQuVfAflqlolS0W/PruWxmPuFIi+D6kNB1SXmd55geG6p/EI4qrZCwyy1fVXFL3WRb 46SWR7xrHvPyaa+WE+J0uzVXOaNjzgl3k7ufjkfaLsz+OvUEt78sg3+E3XyN/+pZZ81nX3p4 /0TXBOv7Ee+UWIozEg21mIuKEwFdrKipQwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjk+LIzCtJLcpLzFFi42I5/e+xoG7W8cOBBocfS1k0/9/OavF30jF2 iyVNGRYvD2laHJj9kNXi1ZmNbBaXF15itfh+w9Sid8FVNotNj6+xWlzeNYfN4uy842wWM87v Y7LYOPUXo0X7JWWLFU1bGS0WX1zObLF+xmsWi90rl7BYHJuxhNHi6YMmJgdRjzXz1jB6/P41 idGjb8pVNo8nmy4yeizYVOpx59oeNo/NS+o9zs9YyOjxfUcvUMGWVYweP1/qeDz9sZfZ4/Mm uQDeqAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zByg d5UUyhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhHWMGTdP97EU3OeveNSd3sC4 h6eLkZNDQsBE4uf9a+wQtpjEhXvr2boYuTiEBKYzSsy68Z4RwvnFKDH3yiUWkCo2ATWJL18O g3WICPhLXLvaygJSxCzQwSaxad4mVpCEsEC4xNTtX4C6OThYBFQlmibZgoR5BSwlrl74yA5h C0r8mHwPbCazgJbE+p3HmSBseYnNa94yQ1ykILHj7GtGiF16Er8/fGeFqBGR2PfiHeMERoFZ SEbNQjJqFpJRs5C0LGBkWcUomlqQXFCclJ5rqFecmFtcmpeul5yfu4kRnLqeSe1gXNlgcYhR gINRiYd3hcrhQCHWxLLiytxDjBIczEoivGITgUK8KYmVValF+fFFpTmpxYcYk4EencgsJZqc D0yreSXxhsYmZkaWRmYWRibm5qQJK4nzHmi1DhQSSE8sSc1OTS1ILYLZwsTBKdXA2H30kiaj vvTfq4f98p5YvfsUWj/Zvd1ATPotzwYutxsnJW5EaW84e+O56g42g1+TC7s4l5b2L2Hfadkd LZ75o+noXv4ZG/iaT01/IThZTdZI/hZroWzXFWeles+jXhHiymEvXqtkveOSMKlN5t4iv/mu 4JKGf/0rNmQlvzXapBR1767/+g9nlViKMxINtZiLihMBAMeXzKEDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Exynos5440 has two PCIe controllers which can be used as root complex for PCIe interface. Signed-off-by: Jingoo Han Acked-by: Arnd Bergmann --- arch/arm/boot/dts/exynos5440.dtsi | 38 +++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 03d40c0..1ac4f5b 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -230,4 +230,42 @@ clocks = <&clock 24>; clock-names = "usbhost"; }; + + pcie@290000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x290000 0x1000 + 0x270000 0x1000 + 0x271000 0x40>; + interrupts = <0 20 0>, <0 21 0>, <0 22 0>; + clocks = <&clock 28>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 53>; + }; + + pcie@2a0000 { + compatible = "samsung,exynos5440-pcie", "snps,dw-pcie"; + reg = <0x2a0000 0x1000 + 0x272000 0x1000 + 0x271040 0x40>; + interrupts = <0 23 0>, <0 24 0>, <0 25 0>; + clocks = <&clock 29>, <&clock 27>; + clock-names = "pcie", "pcie_bus"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */ + 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */ + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 56>; + }; };