From patchwork Tue Dec 10 22:22:07 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 299476 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 142572C0399 for ; Wed, 11 Dec 2013 09:22:37 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751321Ab3LJWWN (ORCPT ); Tue, 10 Dec 2013 17:22:13 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:22171 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751224Ab3LJWWJ (ORCPT ); Tue, 10 Dec 2013 17:22:09 -0500 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MXM005YW3GWSZ40@mailout1.samsung.com> for linux-pci@vger.kernel.org; Wed, 11 Dec 2013 07:22:08 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.47]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id B0.0C.16251.01497A25; Wed, 11 Dec 2013 07:22:08 +0900 (KST) X-AuditID: cbfee691-b7fd26d000003f7b-d2-52a79410db8d Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id A8.CA.15903.01497A25; Wed, 11 Dec 2013 07:22:08 +0900 (KST) Received: from DOJG1HAN03 ([12.23.120.99]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MXM001O53GVU620@mmp2.samsung.com>; Wed, 11 Dec 2013 07:22:08 +0900 (KST) From: Jingoo Han To: 'Marek Vasut' , 'Tim Harvey' Cc: 'Pratyush Anand' , 'Arnd Bergmann' , 'Mohit KUMAR DCG' , 'Richard Zhu' , 'Kishon Vijay Abraham I' , linux-pci@vger.kernel.org, 'Jingoo Han' References: <20131205050424.GA2298@pratyush-vbox> <201312061546.23981.arnd@arndb.de> <20131209071241.GA5760@pratyush-vbox> <201312101426.40614.marex@denx.de> In-reply-to: <201312101426.40614.marex@denx.de> Subject: Re: [Query/Discussion]: IO translation with designware PCIe controller Date: Wed, 11 Dec 2013 07:22:07 +0900 Message-id: <001101cef5f6$4347c520$c9d74f60$%han@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac71un/3jLqtMY2vQ4W3y9iSQKb5/QAOvuYw Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmpgleLIzCtJLcpLzFFi42I5/e+Zvq7AlOVBBu1/+S3+TjrGbvHykKbF h+frWSwuL7zEanHhaQ+bxdl5x9ks3rQ1MlpsnPqL0aL9krLFxROfmB24PH7/msToMW/WCRaP f4f7mTzO9dxl8+jbsorR4+mPvcwex29sZ/L4vEkugCOKyyYlNSezLLVI3y6BK6P15mOWghvi FdMf72JsYNwk3MXIySEhYCJxcc1OFghbTOLCvfVsXYxcHEICyxgl3u3dyAZTtGTXbCaIxHRG ieUztzJCOL8YJfZ9a2MFqWITUJP48uUwO4gtIuAucWTWLhaQImaByUwSs5bdZYboWMgo8WfL R2aQKk4BfYn5K++BdQgL+Et0v5oOFmcRUJXYeeUuI4jNK2Ar8WjlJDYIW1Dix+R7YMcyC2hJ rN95nAnClpfYvOYtUC8H0K3qEo/+6kIcYSSx/vlzVogSEYl9L96BXS0hMJND4mDPTqhdAhLf Jh9igeiVldh0gBniZUmJgytusExglJiFZPMsJJtnIdk8C8mKBYwsqxhFUwuSC4qT0otM9YoT c4tL89L1kvNzNzFCYn/iDsb7B6wPMSYDrZ/ILCWanA9MHXkl8YbGZkYWpiamxkbmlmakCSuJ 86Y/SgoSEkhPLEnNTk0tSC2KLyrNSS0+xMjEwSnVwOjHm3ctjeFe5NNIx6lTHNo2RstXna1Z eEKy++2JQK3HK0NvLq6rPBgazli5oND49JFnv63M47982nw9p2lDn6Otxq+9OluL2urWVy+S enfwXt3Ktk7+ard2VutuoSSj/caMe+WT09JuHmWMyZlzcf7/R89epMtMjb+btKAps27vpe3c El+PX1FiKc5INNRiLipOBAA8upQbEwMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLKsWRmVeSWpSXmKPExsVy+t9jQV2BKcuDDD4s5rL4O+kYu8XLQ5oW H56vZ7G4vPASq8WFpz1sFmfnHWezeNPWyGixceovRov2S8oWF098Ynbg8vj9axKjx7xZJ1g8 /h3uZ/I413OXzaNvyypGj6c/9jJ7HL+xncnj8ya5AI6oBkabjNTElNQihdS85PyUzLx0WyXv 4HjneFMzA0NdQ0sLcyWFvMTcVFslF58AXbfMHKAblRTKEnNKgUIBicXFSvp2mCaEhrjpWsA0 Ruj6hgTB9RgZoIGEdYwZrTcfsxTcEK+Y/ngXYwPjJuEuRk4OCQETiSW7ZjNB2GISF+6tZ+ti 5OIQEpjOKLF85lZGCOcXo8S+b22sIFVsAmoSX74cZgexRQTcJY7M2sUCUsQsMJlJYtayu8wQ HQsZJf5s+cgMUsUpoC8xf+U9sA5hAX+J7lfTweIsAqoSO6/cZQSxeQVsJR6tnMQGYQtK/Jh8 jwXEZhbQkli/8zgThC0vsXnNW6BeDqBb1SUe/dWFOMJIYv3z56wQJSIS+168Y5zAKDQLyaRZ SCbNQjJpFpKWBYwsqxhFUwuSC4qT0nON9IoTc4tL89L1kvNzNzGCE8sz6R2MqxosDjEKcDAq 8fAeKFoeJMSaWFZcmXuIUYKDWUmEd6MpUIg3JbGyKrUoP76oNCe1+BBjMtCjE5mlRJPzgUkv ryTe0NjEzMjSyMzCyMTcnDRhJXHeg63WgUIC6YklqdmpqQWpRTBbmDg4pRoYsx43yLwNc/73 QDg6K/JDtqpA7YWg3Sz995iPtkdzOvy811lRx96hH8EVeemGYecbYGp6NHfGn4rw5fFXFzWv yTJYf9Zmpugzzf2K7nw6gt0WNvrO72L9jBT82b9e3vfy7Y+UqVxTr6/Y4at7Q7+Uq2pTnXLK Swfzzx29TwT+KlQIpSpPXaPEUpyRaKjFXFScCABje6sdcAMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tuesday, December 10, 2013 10:27 PM, Marek Vasut wrote: > On Monday, December 09, 2013 at 08:12:42 AM, Pratyush Anand wrote: [.....] > > > > diff --git a/drivers/pci/host/pcie-designware.c > > b/drivers/pci/host/pcie-designware.c index be6ce30..cf68632 100644 > > --- a/drivers/pci/host/pcie-designware.c > > +++ b/drivers/pci/host/pcie-designware.c > > @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) > > + global_io_offset); > > pp->config.io_size = resource_size(&pp->io); > > pp->config.io_bus_addr = range.pci_addr; > > + pp->io_base = range.cpu_addr; > > } > > if (restype == IORESOURCE_MEM) { > > of_pci_range_to_resource(&range, np, &pp->mem); > > @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) > > > > pp->cfg0_base = pp->cfg.start; > > pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; > > - pp->io_base = pp->io.start; > > pp->mem_base = pp->mem.start; > > > > pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, > > @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data > > *sys) > > > > if (global_io_offset < SZ_1M && pp->config.io_size > 0) { > > sys->io_offset = global_io_offset - pp->config.io_bus_addr; > > - pci_ioremap_io(sys->io_offset, pp->io.start); > > + pci_ioremap_io(sys->io_offset, pp->io_base); > > global_io_offset += SZ_64K; > > pci_add_resource_offset(&sys->resources, &pp->io, > > sys->io_offset); > > Tim, can you test if this patch fixes your SKY2 IOspace problem please ? Above mentioned patch is NOT the latest patch. Pratyush Anand already submitted the next patch as below. Tim, Would you test the following patch on i.MX6 platform? Best regards, Jingoo Han --- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index be6ce30..b83f5e8 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -378,6 +378,7 @@ int __init dw_pcie_host_init(struct pcie_port *pp) + global_io_offset); pp->config.io_size = resource_size(&pp->io); pp->config.io_bus_addr = range.pci_addr; + pp->io_base = range.cpu_addr; } if (restype == IORESOURCE_MEM) { of_pci_range_to_resource(&range, np, &pp->mem); @@ -403,7 +404,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) pp->cfg0_base = pp->cfg.start; pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; - pp->io_base = pp->io.start; pp->mem_base = pp->mem.start; pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, @@ -667,7 +667,7 @@ static int dw_pcie_setup(int nr, struct pci_sys_data *sys) if (global_io_offset < SZ_1M && pp->config.io_size > 0) { sys->io_offset = global_io_offset - pp->config.io_bus_addr; - pci_ioremap_io(sys->io_offset, pp->io.start); + pci_ioremap_io(global_io_offset, pp->io_base); global_io_offset += SZ_64K; pci_add_resource_offset(&sys->resources, &pp->io, sys->io_offset);