| Message ID | 20201230120515.2348-1-nadeem@cadence.com |
|---|---|
| Headers | show |
| Series | PCI: cadence: Retrain Link to work around Gen2 | expand |
Hello, Requesting to provide review comments. Thanks & Regards, Nadeem Athani > -----Original Message----- > From: Nadeem Athani <nadeem@cadence.com> > Sent: Wednesday, December 30, 2020 5:35 PM > To: Tom Joseph <tjoseph@cadence.com>; lorenzo.pieralisi@arm.com; > robh@kernel.org; bhelgaas@google.com; kishon@ti.com; linux- > omap@vger.kernel.org; linux-pci@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Cc: Athani Nadeem Ladkhan <nadeem@cadence.com>; Milind Parab > <mparab@cadence.com>; Swapnil Kashinath Jakhade > <sjakhade@cadence.com>; Parshuram Raju Thombare > <pthombar@cadence.com> > Subject: [PATCH v7 0/2] PCI: cadence: Retrain Link to work around Gen2 > > Cadence controller will not initiate autonomous speed change if strapped as > Gen2. The Retrain Link bit is set as quirk to enable this speed change. > Adding a quirk flag for defective IP. In future IP revisions this will not be > applicable. > > Version history: > Changes in v7: > - Changing the commit title of patch 1 in this series. > - Added a return value for function cdns_pcie_retrain(). > Changes in v6: > - Move the position of function cdns_pcie_host_wait_for_link to remove > compilation error. No changes in code. Separate patch for this. > Changes in v5: > - Remove the compatible string based setting of quirk flag. > - Removed additional Link Up Check > - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c Changes > in v4: > - Added a quirk flag based on a new compatible string. > - Change of api for link up: cdns_pcie_host_wait_for_link(). > Changes in v3: > - To set retrain link bit,checking device capability & link status. > - 32bit read in place of 8bit. > - Minor correction in patch comment. > - Change in variable & macro name. > Changes in v2: > - 16bit read in place of 8bit. > > Nadeem Athani (2): > PCI: cadence: Shifting of a function to support new code. > PCI: cadence: Retrain Link to work around Gen2 training defect. > > drivers/pci/controller/cadence/pci-j721e.c | 3 + > drivers/pci/controller/cadence/pcie-cadence-host.c | 70 ++++++++++++++++- > ----- > drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- > 3 files changed, 65 insertions(+), 19 deletions(-) > > -- > 2.15.0
On 30/12/20 5:35 pm, Nadeem Athani wrote: > Cadence controller will not initiate autonomous speed change if strapped > as Gen2. The Retrain Link bit is set as quirk to enable this speed change. > Adding a quirk flag for defective IP. In future IP revisions this will not > be applicable. > > Version history: > Changes in v7: > - Changing the commit title of patch 1 in this series. > - Added a return value for function cdns_pcie_retrain(). > Changes in v6: > - Move the position of function cdns_pcie_host_wait_for_link to remove > compilation error. No changes in code. Separate patch for this. > Changes in v5: > - Remove the compatible string based setting of quirk flag. > - Removed additional Link Up Check > - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c > Changes in v4: > - Added a quirk flag based on a new compatible string. > - Change of api for link up: cdns_pcie_host_wait_for_link(). > Changes in v3: > - To set retrain link bit,checking device capability & link status. > - 32bit read in place of 8bit. > - Minor correction in patch comment. > - Change in variable & macro name. > Changes in v2: > - 16bit read in place of 8bit. Could get GEN2 card enumerated in GEN2 mode in J7ES EVM. Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Thanks Kishon > > Nadeem Athani (2): > PCI: cadence: Shifting of a function to support new code. > PCI: cadence: Retrain Link to work around Gen2 training defect. > > drivers/pci/controller/cadence/pci-j721e.c | 3 + > drivers/pci/controller/cadence/pcie-cadence-host.c | 70 ++++++++++++++++------ > drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- > 3 files changed, 65 insertions(+), 19 deletions(-) >
Hi Rob / Thomas, Requesting to provide your reviews. Thanks & Regards, Nadeem Athani > -----Original Message----- > From: Kishon Vijay Abraham I <kishon@ti.com> > Sent: Tuesday, January 12, 2021 12:46 PM > To: Athani Nadeem Ladkhan <nadeem@cadence.com>; Tom Joseph > <tjoseph@cadence.com>; lorenzo.pieralisi@arm.com; robh@kernel.org; > bhelgaas@google.com; linux-omap@vger.kernel.org; linux- > pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- > kernel@vger.kernel.org > Cc: Milind Parab <mparab@cadence.com>; Swapnil Kashinath Jakhade > <sjakhade@cadence.com>; Parshuram Raju Thombare > <pthombar@cadence.com> > Subject: Re: [PATCH v7 0/2] PCI: cadence: Retrain Link to work around Gen2 > > EXTERNAL MAIL > > > > > On 30/12/20 5:35 pm, Nadeem Athani wrote: > > Cadence controller will not initiate autonomous speed change if > > strapped as Gen2. The Retrain Link bit is set as quirk to enable this speed > change. > > Adding a quirk flag for defective IP. In future IP revisions this will > > not be applicable. > > > > Version history: > > Changes in v7: > > - Changing the commit title of patch 1 in this series. > > - Added a return value for function cdns_pcie_retrain(). > > Changes in v6: > > - Move the position of function cdns_pcie_host_wait_for_link to remove > > compilation error. No changes in code. Separate patch for this. > > Changes in v5: > > - Remove the compatible string based setting of quirk flag. > > - Removed additional Link Up Check > > - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c > > Changes in v4: > > - Added a quirk flag based on a new compatible string. > > - Change of api for link up: cdns_pcie_host_wait_for_link(). > > Changes in v3: > > - To set retrain link bit,checking device capability & link status. > > - 32bit read in place of 8bit. > > - Minor correction in patch comment. > > - Change in variable & macro name. > > Changes in v2: > > - 16bit read in place of 8bit. > > Could get GEN2 card enumerated in GEN2 mode in J7ES EVM. > > Tested-by: Kishon Vijay Abraham I <kishon@ti.com> > > Thanks > Kishon > > > > Nadeem Athani (2): > > PCI: cadence: Shifting of a function to support new code. > > PCI: cadence: Retrain Link to work around Gen2 training defect. > > > > drivers/pci/controller/cadence/pci-j721e.c | 3 + > > drivers/pci/controller/cadence/pcie-cadence-host.c | 70 > ++++++++++++++++------ > > drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- > > 3 files changed, 65 insertions(+), 19 deletions(-) > >
> -----Original Message----- > From: Nadeem Athani <nadeem@cadence.com> > Sent: 30 December 2020 12:05 > To: Tom Joseph <tjoseph@cadence.com>; lorenzo.pieralisi@arm.com; > robh@kernel.org; bhelgaas@google.com; kishon@ti.com; linux- > omap@vger.kernel.org; linux-pci@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Cc: Athani Nadeem Ladkhan <nadeem@cadence.com>; Milind Parab > <mparab@cadence.com>; Swapnil Kashinath Jakhade > <sjakhade@cadence.com>; Parshuram Raju Thombare > <pthombar@cadence.com> > Subject: [PATCH v7 0/2] PCI: cadence: Retrain Link to work around Gen2 > > Cadence controller will not initiate autonomous speed change if strapped > as Gen2. The Retrain Link bit is set as quirk to enable this speed change. > Adding a quirk flag for defective IP. In future IP revisions this will not > be applicable. > > Version history: > Changes in v7: > - Changing the commit title of patch 1 in this series. > - Added a return value for function cdns_pcie_retrain(). > Changes in v6: > - Move the position of function cdns_pcie_host_wait_for_link to remove > compilation error. No changes in code. Separate patch for this. > Changes in v5: > - Remove the compatible string based setting of quirk flag. > - Removed additional Link Up Check > - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c > Changes in v4: > - Added a quirk flag based on a new compatible string. > - Change of api for link up: cdns_pcie_host_wait_for_link(). > Changes in v3: > - To set retrain link bit,checking device capability & link status. > - 32bit read in place of 8bit. > - Minor correction in patch comment. > - Change in variable & macro name. > Changes in v2: > - 16bit read in place of 8bit. > > Nadeem Athani (2): > PCI: cadence: Shifting of a function to support new code. > PCI: cadence: Retrain Link to work around Gen2 training defect. > > drivers/pci/controller/cadence/pci-j721e.c | 3 + > drivers/pci/controller/cadence/pcie-cadence-host.c | 70 > ++++++++++++++++------ > drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- > 3 files changed, 65 insertions(+), 19 deletions(-) Reviewed-by: Tom Joseph <tjoseph@cadence.com> Thanks, Tom
Hi Lorenzo, Rob, On 12/01/21 12:45 pm, Kishon Vijay Abraham I wrote: > > > On 30/12/20 5:35 pm, Nadeem Athani wrote: >> Cadence controller will not initiate autonomous speed change if strapped >> as Gen2. The Retrain Link bit is set as quirk to enable this speed change. >> Adding a quirk flag for defective IP. In future IP revisions this will not >> be applicable. >> >> Version history: >> Changes in v7: >> - Changing the commit title of patch 1 in this series. >> - Added a return value for function cdns_pcie_retrain(). >> Changes in v6: >> - Move the position of function cdns_pcie_host_wait_for_link to remove >> compilation error. No changes in code. Separate patch for this. >> Changes in v5: >> - Remove the compatible string based setting of quirk flag. >> - Removed additional Link Up Check >> - Removed quirk from pcie-cadence-plat.c and added in pci-j721e.c >> Changes in v4: >> - Added a quirk flag based on a new compatible string. >> - Change of api for link up: cdns_pcie_host_wait_for_link(). >> Changes in v3: >> - To set retrain link bit,checking device capability & link status. >> - 32bit read in place of 8bit. >> - Minor correction in patch comment. >> - Change in variable & macro name. >> Changes in v2: >> - 16bit read in place of 8bit. > > Could get GEN2 card enumerated in GEN2 mode in J7ES EVM. > > Tested-by: Kishon Vijay Abraham I <kishon@ti.com> Can this series be merged? Thanks Kishon > > Thanks > Kishon >> >> Nadeem Athani (2): >> PCI: cadence: Shifting of a function to support new code. >> PCI: cadence: Retrain Link to work around Gen2 training defect. >> >> drivers/pci/controller/cadence/pci-j721e.c | 3 + >> drivers/pci/controller/cadence/pcie-cadence-host.c | 70 ++++++++++++++++------ >> drivers/pci/controller/cadence/pcie-cadence.h | 11 +++- >> 3 files changed, 65 insertions(+), 19 deletions(-) >>