From patchwork Wed Nov 25 10:11:50 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wan Ahmad Zainie X-Patchwork-Id: 1405996 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CgxZ15sRwz9sSf for ; Wed, 25 Nov 2020 21:14:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726357AbgKYKNo (ORCPT ); Wed, 25 Nov 2020 05:13:44 -0500 Received: from mga18.intel.com ([134.134.136.126]:62024 "EHLO mga18.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725838AbgKYKNo (ORCPT ); Wed, 25 Nov 2020 05:13:44 -0500 IronPort-SDR: /8VKirF9TthhmehIVzyzM4e5QPZirEnMdc+iqXjYINaL6pSF0+bst/zn/MIOEsLtEBnJUxbidD cBAIR5ZauSkA== X-IronPort-AV: E=McAfee;i="6000,8403,9815"; a="159873319" X-IronPort-AV: E=Sophos;i="5.78,368,1599548400"; d="scan'208";a="159873319" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Nov 2020 02:13:42 -0800 IronPort-SDR: X7cXxIHQYuVe02sYkNd9+vp+4TQJni7yLRsCW23kSYMDnz/7Hy64q4S/k1px3v8nMSn2I8swES /oMYwl106M2A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.78,368,1599548400"; d="scan'208";a="547216330" Received: from wwanmoha-ilbpg2.png.intel.com ([10.88.227.42]) by orsmga005.jf.intel.com with ESMTP; 25 Nov 2020 02:13:40 -0800 From: Wan Ahmad Zainie To: bhelgaas@google.com, robh+dt@kernel.org, lorenzo.pieralisi@arm.com Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@linux.intel.com, mgross@linux.intel.com, lakshmi.bai.raja.subramanian@intel.com, wan.ahmad.zainie.wan.mohamad@intel.com Subject: [PATCH v2 0/2] PCI: keembay: Add support for Intel Keem Bay Date: Wed, 25 Nov 2020 18:11:50 +0800 Message-Id: <20201125101152.5326-1-wan.ahmad.zainie.wan.mohamad@intel.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi. The first patch is to document DT bindings for Keem Bay PCIe controller for both Root Complex and Endpoint modes. The second patch is the driver file, a glue driver. Keem Bay PCIe controller is based on DesignWare PCIe IP. The patch was tested with Keem Bay evaluation module board, with A0 stepping. Thank you. Best regards, Zainie Changes since v1: - In dt-bindings patch. - Fixed indent warning for compatible property. - Rename interrupt-names to pcie, pcie_ev, pcie_err and pcie_mem_access, similar to the name used in datasheet. - Remove device_type, #address-cells and #size-cells property. - Remove num-viewport, num-ib-windows and num-ob-windows property. - Replace additionalProperties with unevaluatedProperties, for RC only. - Add dbi2 and atu property. - Remove description for regs and interrupts property. - Change enum value for num-lanes to 1 and 2 only. - In driver patch. - In Kconfig file, remove dependency on ARM64. - Add new define, PCIE_REGS_PCIE_SII_LINK_UP. - Remove PCIE_DBI2_MASK. - In struct keembay_pcie, declare pci member as struct, not pointer. And remove irq number members. - Rename and rework keembay_pcie_establish_link(), to keembay_pcie_start_link(). - Remove unneeded BAR disable steps. - Remove unused interrupt handlers; keembay_pcie_ev_irq_handler(), keembay_pcie_err_irq_handler(). - Remove keembay_pcie_enable_interrupts(). - Rework keembay_pcie_setup_irq() and call it from keembay_pcie_probe(). - Remove keembay_pcie_host_init() and make keembay_pcie_host_ops empty. - Keep and rework keembay_pcie_add_pcie_port() a little. - Remove keembay_pcie_add_pcie_ep() and call dw_pcie_ep_init() from keembay_pcie_probe(). - In keembay_pcie_probe(), remove dbi setup as it will be handled in dwc common code. - In keembay_pcie_link_up(), use return (val & PCIE_REGS_PCIE_SII_LINK_UP) == PCIE_REGS_PCIE_SII_LINK_UP. - In keembay_pcie_ep_raise_irq(), rework error message for PCI_EPC_IRQ_LEGACY and default cases. - Rebased to next-20201124, that has dwc pci refactoring, https://lore.kernel.org/linux-pci/20201105211159.1814485-1-robh@kernel.org/. Wan Ahmad Zainie (2): dt-bindings: PCI: Add Intel Keem Bay PCIe controller PCI: keembay: Add support for Intel Keem Bay .../bindings/pci/intel,keembay-pcie-ep.yaml | 68 +++ .../bindings/pci/intel,keembay-pcie.yaml | 96 ++++ drivers/pci/controller/dwc/Kconfig | 24 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-keembay.c | 505 ++++++++++++++++++ 5 files changed, 694 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/intel,keembay-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-keembay.c