[00/30] Enable Tegra PCIe root port features

Message ID	20190411170355.6882-1-mmaddireddy@nvidia.com
Headers	show Return-Path: <linux-pci-owner@vger.kernel.org> TLS: TLSv1.2, DES-CBC3-SHA) id <B5caf739e0000>; Thu, 11 Apr 2019 10:04:30 -0700 From: Manikanta Maddireddy <mmaddireddy@nvidia.com> To: <thierry.reding@gmail.com>, <bhelgaas@google.com>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com> CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>, Manikanta Maddireddy <mmaddireddy@nvidia.com> Subject: [PATCH 00/30] Enable Tegra PCIe root port features Date: Thu, 11 Apr 2019 22:33:25 +0530 Message-ID: <20190411170355.6882-1-mmaddireddy@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-pci-owner@vger.kernel.org Precedence: bulk
Series	Enable Tegra PCIe root port features \| expand [00/30] Enable Tegra PCIe root port features [01/30] soc/tegra: pmc: Export tegra_powergate_power_on() [02/30] PCI: tegra: Fix PCIe host power up sequence [03/30] PCI: tegra: Move REFCLK pad settings out of phy_power_on() [04/30] PCI: tegra: Add PCIe Gen2 link speed support [05/30] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability [06/30] PCI: tegra: Program UPHY electrical settings for Tegra210 [07/30] PCI: tegra: Enable opportunistic update FC and ACK [08/30] PCI: tegra: Disable AFI dynamic clock gating [09/30] PCI: tegra: Process pending DLL transactions before entering L1 or L2 [10/30] PCI: tegra: Enable PCIe xclk clock clamping [11/30] PCI: tegra: Increase the deskew retry time [12/30] PCI: tegra: Add SW fixup for RAW violations [13/30] PCI: tegra: Update flow control threshold in Tegra210 [14/30] PCI: tegra: Set target speed as Gen1 before link up [15/30] PCI: tegra: Fix PLLE powerdown issue due to CLKREQ# signal [16/30] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 [17/30] PCI: tegra: Use switch statements in tegra_pcie_isr() [18/30] PCI: tegra: Change PRSNT_SENSE irq log to debug [19/30] PCI: tegra: Use legacy irq for port service drivers [20/30] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct [21/30] PCI: tegra: Add "pci" type check before parsing child device tree node [22/30] PCI: tegra: Access endpoint config only if PCIe link is up [23/30] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop [24/30] arm64: tegra: Add PEX DPD states as pinctrl properties [25/30] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode [26/30] dt-bindings: pci: tegra: Document nvidia,plat-gpios optional prop [27/30] PCI: tegra: Add support to configure platform GPIOs [28/30] dt-bindings: pci: tegra: Document nvidia,rst-gpio optional prop [29/30] PCI: tegra: Add support for GPIO based PCIe reset [30/30] PCI: tegra: Change link retry log level to INFO

Message ID

20190411170355.6882-1-mmaddireddy@nvidia.com

Headers

From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <thierry.reding@gmail.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<jonathanh@nvidia.com>, <lorenzo.pieralisi@arm.com>, <vidyas@nvidia.com>
CC: <linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>,
	Manikanta Maddireddy <mmaddireddy@nvidia.com>
Subject: [PATCH 00/30] Enable Tegra PCIe root port features
Date: Thu, 11 Apr 2019 22:33:25 +0530
Message-ID: <20190411170355.6882-1-mmaddireddy@nvidia.com>
MIME-Version: 1.0
Content-Type: text/plain
Sender: linux-pci-owner@vger.kernel.org
Precedence: bulk

Series

Enable Tegra PCIe root port features | expand

Message

Manikanta Maddireddy April 11, 2019, 5:03 p.m. UTC

This series of patches adds,
- Tegra root port features like Gen2, AER, etc
- Power and perf optimizations
- Fixes like "power up sequence", "dev_err prints", etc

These series of patches are tested on Tegra186 based Jetson-TX2, Tegra210
based Jetson-TX1 and T124 based Jetson-TK1 platforms.

Manikanta Maddireddy (30):
  soc/tegra: pmc: Export tegra_powergate_power_on()
  PCI: tegra: Fix PCIe host power up sequence
  PCI: tegra: Move REFCLK pad settings out of phy_power_on()
  PCI: tegra: Add PCIe Gen2 link speed support
  PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability
  PCI: tegra: Program UPHY electrical settings for Tegra210
  PCI: tegra: Enable opportunistic update FC and ACK
  PCI: tegra: Disable AFI dynamic clock gating
  PCI: tegra: Process pending DLL transactions before entering L1 or L2
  PCI: tegra: Enable PCIe xclk clock clamping
  PCI: tegra: Increase the deskew retry time
  PCI: tegra: Add SW fixup for RAW violations
  PCI: tegra: Update flow control threshold in Tegra210
  PCI: tegra: Set target speed as Gen1 before link up
  PCI: tegra: Fix PLLE powerdown issue due to CLKREQ# signal
  PCI: tegra: Program AFI_CACHE* registers only for Tegra20
  PCI: tegra: Use switch statements in tegra_pcie_isr()
  PCI: tegra: Change PRSNT_SENSE irq log to debug
  PCI: tegra: Use legacy irq for port service drivers
  PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct
  PCI: tegra: Add "pci" type check before parsing child device tree node
  PCI: tegra: Access endpoint config only if PCIe link is up
  dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop
  arm64: tegra: Add PEX DPD states as pinctrl properties
  PCI: tegra: Put PEX CLK & BIAS pads in DPD mode
  dt-bindings: pci: tegra: Document nvidia,plat-gpios optional prop
  PCI: tegra: Add support to configure platform GPIOs
  dt-bindings: pci: tegra: Document nvidia,rst-gpio optional prop
  PCI: tegra: Add support for GPIO based PCIe reset
  PCI: tegra: Change link retry log level to INFO

 .../bindings/pci/nvidia,tegra20-pcie.txt      |  15 +
 arch/arm64/boot/dts/nvidia/tegra210.dtsi      |  19 +
 drivers/pci/controller/pci-tegra.c            | 696 ++++++++++++++++--
 drivers/soc/tegra/pmc.c                       |   1 +
 4 files changed, 656 insertions(+), 75 deletions(-)