From patchwork Tue Oct 31 04:22:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 832232 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yQyv950xlz9t2l for ; Tue, 31 Oct 2017 15:25:25 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751192AbdJaEZY (ORCPT ); Tue, 31 Oct 2017 00:25:24 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:6036 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751119AbdJaEZX (ORCPT ); Tue, 31 Oct 2017 00:25:23 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Mon, 30 Oct 2017 21:24:43 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 30 Oct 2017 21:25:03 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 30 Oct 2017 21:25:03 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Tue, 31 Oct 2017 04:22:54 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Tue, 31 Oct 2017 04:22:54 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.36.185]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 30 Oct 2017 21:22:53 -0700 From: Vidya Sagar To: , , , , , CC: , , , , Subject: [PATCH V2 0/4] Add ASPM-L1 Substates support for Tegra Date: Tue, 31 Oct 2017 09:52:45 +0530 Message-ID: <1509423769-10522-1-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Tegra chips T210 and T186 support ASPM-L1 Substates (i.e. L1.1 and L1.2) This patch series - adds a generic API for root port controller drivers to override the default value of LTR L1.2 Threhold which otherwise comes from the same APIs weak implementation in aspm.c file - applies fixups to reflect correct capability values for T_cmrt (Common Mode Restore Time) and T_pwr_on (Power On) and adjusts counter values for 19.2 MHz of clk_m - applies fixup specific to T210 to avoid unnecessary wake ups from L1.2 state PCIe - ASPM L1 Sub States spec https://pcisig.com/sites/default/files/specification_documents/ECN_L1_PM_Substates_with_CLKREQ_31_May_2013_Rev10a.pdf Testing Done on T210 and T186 - ASPM-L1: Verified ASPM-L1 enablement by selecting PCIEASPM_POWERSAVE config With the help of Tegra rootport's internal counter registers, confirmed link entry in and out of ASPM-L1 state using USB3.0 add-on card, NVMe and NIC cards - ASPM-L1 SubStates: Verified ASPM-L1 Substates enablement by selecting PCIEASPM_POWER_SUPERSAVE config Confirmed link's entry into L1SS using Westren Digital NVMe card (with Sandisk Controller) using Tegra rootport's internal counter registers Vidya Sagar (4): PCI/ASPM: Add API to supply LTR L1.2 threshold PCI: tegra: Enable ASPM-L1 capability advertisement PCI: tegra: Apply sw fixups to support ASPM-L1 Sub-States PCI: tegra: fixups to avoid unnecessary wakeup from ASPM-L1.2 drivers/pci/host/pci-tegra.c | 99 ++++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pcie/aspm.c | 11 +++-- include/linux/pci-aspm.h | 1 + 3 files changed, 108 insertions(+), 3 deletions(-)