From patchwork Thu May 6 09:08:52 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 51810 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D2E13B7D1A for ; Thu, 6 May 2010 19:10:23 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.69 #1 (Red Hat Linux)) id 1O9x4q-0004Ho-WA; Thu, 06 May 2010 09:09:05 +0000 Received: from mail-pv0-f177.google.com ([74.125.83.177]) by bombadil.infradead.org with esmtp (Exim 4.69 #1 (Red Hat Linux)) id 1O9x4f-00047u-CC; Thu, 06 May 2010 09:08:54 +0000 Received: by pvg16 with SMTP id 16so177573pvg.36 for ; Thu, 06 May 2010 02:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=W6GNvQSEM4I76gBIy9h6M2FDnVLFmV2sPsWYHOrsalo=; b=MwROr0ObpyLFEdoObNF9o6OSXE0mEk86d0ZwCiL8kSKgdU1wDDoer0g/Yb2ckv90R1 AFvjzbbMMPopY9JAR3T/OObDo6apaSM6kz39WSEYR4TFSDDQ6ReiiM24n1aYK+7j0ySo ahBehjN2ecu+A299wyfcQg4rNRH53mj1ASvS4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=Juu2pNuOSnDcj5oXC67fvs7tYO/aMmIbWuwD7Yp2R3Krlj/wCE3cKJM+ImCC9jxDMg qDXr/nVwhPUrHI+ev2FXLIHdi3JEq9bdsnI5/UWCxxtzzdd4b5l2IZxICEOSTXHQEmD8 fF65ewK+uFhUym2EyLIKYDkiVjAhu+po9HWKY= MIME-Version: 1.0 Received: by 10.143.193.8 with SMTP id v8mr3084193wfp.162.1273136932171; Thu, 06 May 2010 02:08:52 -0700 (PDT) Received: by 10.142.252.16 with HTTP; Thu, 6 May 2010 02:08:52 -0700 (PDT) Date: Thu, 6 May 2010 05:08:52 -0400 Message-ID: Subject: [PATCH 11/20] pxa3xx_nand: add debug messege From: Haojian Zhuang To: Eric Miao , linux-arm-kernel , David Woodhouse , linux-mtd@lists.infradead.org X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100506_050853_512161_07A69EF2 X-CRM114-Status: GOOD ( 15.52 ) X-Spam-Score: -0.1 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is freemail (haojian.zhuang[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From 5180a68abe66a42ab389d5234dbbee14dc3fe9b9 Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Tue, 30 Mar 2010 20:58:58 +0800 Subject: [PATCH] pxa3xx_nand: add debug messege Add debug messege to those key route to help find out problem. Signed-off-by: Lei Wen Signed-off-by: Haojian Zhuang --- drivers/mtd/nand/pxa3xx_nand.c | 23 ++++++++++++++++++++++- 1 files changed, 22 insertions(+), 1 deletions(-) DCSR(info->data_dma_ch) |= DCSR_RUN; @@ -505,6 +517,7 @@ static void pxa3xx_nand_data_dma_irq(int channel, void *data) dcsr = DCSR(channel); DCSR(channel) = dcsr; + DBG_NAND(printk("DMA IRQ: dcsr %x\n", dcsr)); if (dcsr & DCSR_BUSERR) { nand->retcode = ERR_DMABUSERR; } @@ -528,6 +541,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) info = nand->info[cs]; status = nand_readl(nand, NDSR); + DBG_NAND(if (status != 0) + printk("\t\tstatus %x, cs %x\n", status, cs)); nand->bad_count = (status & NDSR_ERR_CNT_MASK) >> 16; if (status & NDSR_DBERR) nand->retcode = ERR_DBERR; @@ -562,6 +577,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid) nand_writel(nand, NDCB0, info->ndcb0); nand_writel(nand, NDCB0, info->ndcb1); nand_writel(nand, NDCB0, info->ndcb2); + DBG_NAND(printk("\tndcb0 %x ndcb1 %x ndcb2 %x\n", + info->ndcb0, info->ndcb1, info->ndcb2)); } /* clear NDSR to let the controller exit the IRQ */ @@ -754,6 +771,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command, nand_writel(nand, NDTR1CS0, info->ndtr1cs0); } + DBG_NAND(printk("command %x, page %x\n", command, page_addr)); exec_cmd = prepare_command_pool(nand, command, column, page_addr); if (exec_cmd) { init_completion(&nand->cmd_complete); @@ -940,6 +958,7 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); if (nand->retcode == ERR_SBERR) { + DBG_NAND(printk("###correctable error detected\n");); switch (nand->use_ecc) { case ECC_BCH: if (nand->bad_count > BCH_THRESHOLD) @@ -956,8 +975,10 @@ static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, int buf_blank; buf_blank = is_buf_blank(buf, mtd->writesize); - if (!buf_blank) + if (!buf_blank) { + DBG_NAND(printk("###uncorrectable error!!!\n")); mtd->ecc_stats.failed++; + } } return 0; diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index fb1af4c..0674b52 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -30,6 +30,12 @@ #define NAND_STOP_DELAY (2 * HZ/50) #define PAGE_CHUNK_SIZE (2048) #define BCH_THRESHOLD (8) +#undef PXA3XX_NAND_DEBUG +#ifdef PXA3XX_NAND_DEBUG +#define DBG_NAND(x) do{x;}while(0) +#else +#define DBG_NAND(x) +#endif /* registers and bit definitions */ #define NDCR (0x00) /* Control register */ @@ -411,6 +417,8 @@ static void pxa3xx_nand_start(struct pxa3xx_nand *nand) } /* clear status bits and run */ + DBG_NAND(printk("@@@ndcr set: %x, ndeccctrl set %x\n", + ndcr, ndeccctrl)); nand_writel(nand, NDCR, 0); nand_writel(nand, NDECCCTRL, ndeccctrl); nand_writel(nand, NDSR, NDSR_MASK); @@ -456,6 +464,8 @@ static void handle_data_pio(struct pxa3xx_nand *nand) { struct pxa3xx_nand_info *info = nand->info[nand->chip_select]; + DBG_NAND(printk("data size %x, oob size %x\n", + nand->data_size, nand->oob_size)); if (nand->state & STATE_IS_WRITE) { __raw_writesl(nand->mmio_base + NDDB, info->data_buff, DIV_ROUND_UP(nand->data_size, 4)); @@ -492,6 +502,8 @@ static void start_data_dma(struct pxa3xx_nand *nand, int dir_out) desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC; } + DBG_NAND(printk("DMA START:DMA dcmd %x, dsadr %x, dtadr %x, len %x\n", + desc->dcmd, desc->dsadr, desc->dtadr, dma_len)); DRCMR(nand->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch; DDADR(info->data_dma_ch) = info->data_desc_addr;