From patchwork Thu Sep 29 13:19:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kraemer, Matthias (Ferchau; ADITG/SW1)" X-Patchwork-Id: 676626 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3slFbW09HXz9s3v for ; Thu, 29 Sep 2016 23:21:59 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bpbFw-0003FD-2i; Thu, 29 Sep 2016 13:20:08 +0000 Received: from smtp1.de.adit-jv.com ([62.225.105.245]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bpbFp-0002vC-91 for linux-mtd@lists.infradead.org; Thu, 29 Sep 2016 13:20:05 +0000 Received: from localhost (smtp1.de.adit-jv.com [127.0.0.1]) by smtp1.de.adit-jv.com (Postfix) with ESMTP id B74813C01E2; Thu, 29 Sep 2016 15:19:34 +0200 (CEST) Received: from smtp1.de.adit-jv.com ([127.0.0.1]) by localhost (smtp1.de.adit-jv.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eKqyQmwcemeB; Thu, 29 Sep 2016 15:19:30 +0200 (CEST) Received: from HI2EXCH01.adit-jv.com (hi2exch01.adit-jv.com [10.72.92.24]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp1.de.adit-jv.com (Postfix) with ESMTPS id F1DEF3C01E0; Thu, 29 Sep 2016 15:19:30 +0200 (CEST) Received: from HI2EXCH01.adit-jv.com ([fe80::69bf:8148:2f13:f289]) by HI2EXCH01.adit-jv.com ([fe80::69bf:8148:2f13:f289%12]) with mapi id 14.03.0301.000; Thu, 29 Sep 2016 15:19:31 +0200 From: "Kraemer, Matthias (Ferchau; ADITG/SW1)" To: Mika Westerberg , "linux-mtd@lists.infradead.org" Subject: RE: [PATCH v3 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake SoC Thread-Topic: [PATCH v3 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake SoC Thread-Index: AQHR9sQqsIeCJWUcTUyMjAekyHtFAKCQsaSA Date: Thu, 29 Sep 2016 13:19:30 +0000 Message-ID: References: <1471245044-12767-1-git-send-email-mika.westerberg@linux.intel.com> <1471245044-12767-4-git-send-email-mika.westerberg@linux.intel.com> In-Reply-To: <1471245044-12767-4-git-send-email-mika.westerberg@linux.intel.com> Accept-Language: en-US, de-DE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.72.92.251] MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160929_062001_741328_418BDC33 X-CRM114-Status: GOOD ( 14.79 ) X-Spam-Score: -3.3 (---) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-3.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Woodhouse , "key.seong.lim@intel.com" , "linux-kernel@vger.kernel.org" , Peter Tyser , Brian Norris , Lee Jones Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Hello Mika, In line 1239 you specify "struct pci_bus *bus = dev->bus;" }, @@ -1122,6 +1131,36 @@ static int lpc_ich_init_spi(struct pci_dev *dev) } break; + case INTEL_SPI_BXT: { + unsigned int p2sb = PCI_DEVFN(13, 0); + unsigned int spi = PCI_DEVFN(13, 2); + struct pci_bus *bus = dev->bus; but in line 1262 you are using dev->bus again. + + pci_bus_write_config_byte(dev->bus, p2sb, 0xe1, 0x1); Sure this is not a runtime issue, but it would be nice to keep the coding-style consistent. We could just use dev->bus for BXT SOCs, like the remaining parts of this driver do. Kind regards Matthias Kraemer -----Original Message----- From: linux-kernel-owner@vger.kernel.org [mailto:linux-kernel-owner@vger.kernel.org] On Behalf Of Mika Westerberg Sent: Montag, 15. August 2016 09:11 To: linux-mtd@lists.infradead.org Cc: Brian Norris; David Woodhouse; Lee Jones; Peter Tyser; key.seong.lim@intel.com; Mika Westerberg; linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake SoC Intel Apollo Lake SoC exposes serial SPI flash through the LPC device. The SPI flash host controller is not discoverable through PCI config cycles because P2SB (function 0 of the device 13) is hidden by the BIOS. We unhide the device briefly in order to read BAR 0 of the SPI host controller. Signed-off-by: Mika Westerberg --- drivers/mfd/lpc_ich.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) #define BCR 0xdc #define BCR_WPD BIT(0) +#define SPIBASE_APL_SZ 4096 + #define GPIOBASE_ICH0 0x58 #define GPIOCTRL_ICH0 0x5C #define GPIOBASE_ICH6 0x48 @@ -239,6 +242,7 @@ enum lpc_chipsets { LPC_BRASWELL, /* Braswell SoC */ LPC_LEWISBURG, /* Lewisburg */ LPC_9S, /* 9 Series */ + LPC_APL, /* Apollo Lake SoC */ }; static struct lpc_ich_info lpc_chipset_info[] = { @@ -559,6 +563,10 @@ static struct lpc_ich_info lpc_chipset_info[] = { .name = "9 Series", .iTCO_version = 2, }, + [LPC_APL] = { + .name = "Apollo Lake SoC", + .spi_type = INTEL_SPI_BXT, + }, }; /* @@ -707,6 +715,7 @@ static const struct pci_device_id lpc_ich_ids[] = { { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, + { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL}, { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, @@ -1122,6 +1131,36 @@ static int lpc_ich_init_spi(struct pci_dev *dev) } break; + case INTEL_SPI_BXT: { + unsigned int p2sb = PCI_DEVFN(13, 0); + unsigned int spi = PCI_DEVFN(13, 2); + struct pci_bus *bus = dev->bus; + + /* + * The P2SB is hidden by BIOS and we need to unhide it in + * order to read BAR of the SPI flash device. Once that is + * done we hide it again. + */ + pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0); + pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0, + &spi_base); + if (spi_base != ~0) { + res->start = spi_base & 0xfffffff0; + res->end = res->start + SPIBASE_APL_SZ - 1; + + pci_bus_read_config_dword(bus, spi, BCR, &bcr); + if (!(bcr & BCR_WPD)) { + bcr |= BCR_WPD; + pci_bus_write_config_dword(bus, spi, BCR, bcr); + pci_bus_read_config_dword(bus, spi, BCR, &bcr); + } + info->writeable = !!(bcr & BCR_WPD); + } + + pci_bus_write_config_byte(dev->bus, p2sb, 0xe1, 0x1); + break; + } + default: return -EINVAL; } -- 2.8.1 diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 56a0e98a5f89..b1013b3f4dee 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -56,6 +56,7 @@ * document number TBD : Wildcat Point-LP * document number TBD : 9 Series * document number TBD : Lewisburg + * document number TBD : Apollo Lake SoC */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt @@ -92,6 +93,8 @@