From patchwork Wed Jul 28 05:58:14 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 60105 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 63063B6EEE for ; Wed, 28 Jul 2010 16:06:42 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1Odzl1-0001rU-Eq; Wed, 28 Jul 2010 06:04:49 +0000 Received: from mail-pv0-f177.google.com ([74.125.83.177]) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1Odzeh-0004Cu-80; Wed, 28 Jul 2010 05:58:16 +0000 Received: by pvf33 with SMTP id 33so904095pvf.36 for ; Tue, 27 Jul 2010 22:58:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=bnzIYk8Ua97dbxDuxE4o537+cy0z7Ud8rViJWdc8lFw=; b=JW7yF37HG9LLbGQBF/iNm7ZlgMca08F4SONfLec/8BfG0qNWMW1AfX3fPfZucydH+G ytCYXtx6N/MkKcFj/+n/n7YUVYjaKm/BfME2xMuxrMNGtof2oYJyFBM1QMaxt1n/dWVJ fjl6f98sfIJPE8sX8oeCKGounbK2++p/OjNjQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=dRPHfPn+pxE137Zv5MKN3zXFHv0WZtKKoprkCuM9Xs9tGFkkN8C4pfnBwgrHGLonEk q9UE5b3TP3mKx8oScZLGA0w60nDRCP6l6+ZzgOQQJGTKmBMFHbUcIjrTL7J6tTvOis3/ JIveQKotXFR8D3FfKW6NQa1DaxLyJJcfHioXU= MIME-Version: 1.0 Received: by 10.142.133.20 with SMTP id g20mr4602572wfd.289.1280296694335; Tue, 27 Jul 2010 22:58:14 -0700 (PDT) Received: by 10.142.54.6 with HTTP; Tue, 27 Jul 2010 22:58:14 -0700 (PDT) Date: Wed, 28 Jul 2010 13:58:14 +0800 Message-ID: Subject: [PATCH 21/29] pxa3xx_nand: add ext id check From: Haojian Zhuang To: Eric Miao , linux-arm-kernel , David Woodhouse , David Woodhouse , Marc Kleine-Budde , linux-mtd@lists.infradead.org, Lei Wen X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100728_015815_691374_53770A24 X-CRM114-Status: GOOD ( 17.99 ) X-Spam-Score: -0.1 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, low trust [74.125.83.177 listed in list.dnswl.org] 0.0 FREEMAIL_FROM Sender email is freemail (haojian.zhuang[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From eda41023eeb14c4b41bc5e25765a12e1e99d9ef3 Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Tue, 22 Jun 2010 22:57:04 +0800 Subject: [PATCH 21/29] pxa3xx_nand: add ext id check For K9LBG08U0M and K9LBG08UXD two nand chip, they have the same chip id as 0xd7ec. So we should use the ext id to distinguish them. Signed-off-by: Lei Wen --- arch/arm/plat-pxa/include/plat/pxa3xx_nand.h | 3 +- drivers/mtd/nand/pxa3xx_nand.c | 32 +++++++++++++------------- 2 files changed, 18 insertions(+), 17 deletions(-) +{ "64MiB 16-bit", 0x46ec, 0xffff, 32, 512, 16, 16, ECC_HAMMIN, 4096, NAND_SETTING_SAMSUNG, }, +{ "256MiB 8-bit", 0xdaec, 0xffff, 64, 2048, 8, 8, ECC_HAMMIN, 2048, NAND_SETTING_SAMSUNG, }, +{ "1GiB 8-bit", 0xd3ec, 0xffff, 128, 2048, 8, 8, ECC_BCH, 4096, NAND_SETTING_SAMSUNG, }, +{ "4GiB 8-bit", 0xd7ec, 0x29d5, 128, 4096, 8, 8, ECC_BCH, 8192, NAND_SETTING_SAMSUNG, }, +{ "128MiB 8-bit", 0xa12c, 0xffff, 64, 2048, 8, 8, ECC_HAMMIN, 1024, NAND_SETTING_MICRON, }, +{ "128MiB 16-bit", 0xb12c, 0xffff, 64, 2048, 16, 16, ECC_HAMMIN, 1024, NAND_SETTING_MICRON, }, +{ "512MiB 8-bit", 0xdc2c, 0xffff, 64, 2048, 8, 8, ECC_HAMMIN, 4096, NAND_SETTING_MICRON, }, +{ "512MiB 16-bit", 0xcc2c, 0xffff, 64, 2048, 16, 16, ECC_HAMMIN, 4096, NAND_SETTING_MICRON, }, +{ "1GiB 8-bit", 0x382c, 0xffff, 128, 4096, 8, 8, ECC_BCH, 2048, NAND_SETTING_MICRON }, +{ "256MiB 16-bit", 0xba20, 0xffff, 64, 2048, 16, 16, ECC_HAMMIN, 2048, NAND_SETTING_ST, }, }; static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL}; @@ -1209,7 +1209,7 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd) struct nand_flash_dev pxa3xx_flash_ids[2] = {{NULL,}, {NULL,}}; const struct pxa3xx_nand_flash *f = NULL; struct nand_chip *chip = mtd->priv; - uint32_t id = -1; + uint16_t id[2]; uint64_t chipsize; int i, ret; @@ -1225,10 +1225,10 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd) return -EINVAL; } - nand->data_buff = (unsigned char *)&id; + nand->data_buff = (unsigned char *)id; chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0); - if (id != 0) - dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id); + if (id[0] != 0) + dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id[0]); else { dev_warn(&nand->pdev->dev, "Read out ID 0, potential timing set wrong!!\n"); free_cs_resource(info, nand->chip_select); @@ -1242,7 +1242,7 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd) f = &builtin_flash_types[i - pdata->num_flash + 1]; /* find the chip in default list */ - if (f->chip_id == id) + if ((f->chip_id == id[0]) && ((f->ext_id & id[1]) == id[1])) break; } diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h index ed7d623..c20ac35 100644 --- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h +++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h @@ -37,7 +37,8 @@ struct pxa3xx_nand_cmdset { struct pxa3xx_nand_flash { char *name; - uint32_t chip_id; + uint16_t chip_id; /* chip id */ + uint16_t ext_id; /* Extend id */ uint16_t page_per_block; /* Pages per block */ uint16_t page_size; /* Page size in bytes */ uint8_t flash_width; /* Width of Flash memory (DWIDTH_M) */ diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 048b576..b0a0ccf 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -253,17 +253,17 @@ static struct pxa3xx_nand_timing __devinitdata timing[] = { #define NAND_SETTING_MICRON &default_cmdset, &timing[2] #define NAND_SETTING_ST &default_cmdset, &timing[3] static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = { -{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, ECC_NONE, 0, NAND_SETTING_DEFAULT, }, -{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, ECC_HAMMIN, 4096, NAND_SETTING_SAMSUNG, }, -{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, ECC_HAMMIN, 2048, NAND_SETTING_SAMSUNG, }, -{ "1GiB 8-bit", 0xd3ec, 128, 2048, 8, 8, ECC_BCH, 4096, NAND_SETTING_SAMSUNG, }, -{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, ECC_BCH, 8192, NAND_SETTING_SAMSUNG, }, -{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, ECC_HAMMIN, 1024, NAND_SETTING_MICRON, }, -{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, ECC_HAMMIN, 1024, NAND_SETTING_MICRON, }, -{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, ECC_HAMMIN, 4096, NAND_SETTING_MICRON, }, -{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, ECC_HAMMIN, 4096, NAND_SETTING_MICRON, }, -{ "1GiB 8-bit", 0x382c, 128, 4096, 8, 8, ECC_BCH, 2048, NAND_SETTING_MICRON }, -{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, ECC_HAMMIN, 2048, NAND_SETTING_ST, }, +{ "DEFAULT FLASH", 0, 0, 0, 2048, 8, 8, ECC_NONE, 0, NAND_SETTING_DEFAULT, },