From patchwork Tue Aug 17 12:29:37 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haojian Zhuang X-Patchwork-Id: 61885 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C3689B6EF1 for ; Tue, 17 Aug 2010 22:31:09 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OlLIY-0001io-Nw; Tue, 17 Aug 2010 12:29:46 +0000 Received: from mail-ww0-f49.google.com ([74.125.82.49]) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OlLIU-0001hy-Ih; Tue, 17 Aug 2010 12:29:43 +0000 Received: by wwi14 with SMTP id 14so6974312wwi.18 for ; Tue, 17 Aug 2010 05:29:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:received:date:message-id :subject:from:to:content-type; bh=C30um9dtVvmA1RpFUT24MoFuwEpCyp3iWDnjjg2Kvrg=; b=gJBK1uQ9IUPXZpqAJR1lNsgp84Q6JVCvDzDvaieZ9vf4+luaObs7tlVxr7mgFNu1om xO2k9qEb0M0zSp6DQoldxqS9LSe/SuiFfSgI4yOTURqpZscI0A3iRkhtcL54Lw8FgdMo rKIVD06T3xjQd2ENgc90jFiRbjACVdQ4GGFjY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=fvJa2S2U5d6M+KQsEuayEq1QzmNFpdx0BDyznMa/MS41e6Usu8ZzexIFnQfYx1NyRR LQHRZbEz8eRHHOTn0RBaN+8d0GfIxBYyD2ld6gAngCcVJ1JrOaaFbujfvj+pyhpHWPO0 Fr0nRpdfnWwZVF2hjQzGC8ZhkXez6whrIzmlQ= MIME-Version: 1.0 Received: by 10.227.137.15 with SMTP id u15mr5625131wbt.129.1282048177718; Tue, 17 Aug 2010 05:29:37 -0700 (PDT) Received: by 10.216.46.73 with HTTP; Tue, 17 Aug 2010 05:29:37 -0700 (PDT) Date: Tue, 17 Aug 2010 20:29:37 +0800 Message-ID: Subject: [PATCH 01/06] pxa3xx_nand: update ns2cycle calculation method From: Haojian Zhuang To: Eric Miao , David Woodhouse , linux-mtd@lists.infradead.org, linux-arm-kernel X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100817_082942_766847_7D05C186 X-CRM114-Status: GOOD ( 19.17 ) X-Spam-Score: -0.1 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is freemail (haojian.zhuang[at]gmail.com) -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From 9064b2c877cad560fda7577564b3369c0025b7df Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Tue, 17 Aug 2010 17:24:06 +0800 Subject: [PATCH 01/06] pxa3xx_nand: update ns2cycle calculation method For the original method change from plus 1 to minus 1, this way make the default timing like tCS become 0 after calculation, although we set the timing as 0xa... Change the method to no plus and minus, and make the result closer to what the timing specified in the NAND chip spec. Signed-off-by: Lei Wen --- drivers/mtd/nand/pxa3xx_nand.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) From 9064b2c877cad560fda7577564b3369c0025b7df Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Tue, 17 Aug 2010 17:24:06 +0800 Subject: [PATCH 01/12] pxa3xx_nand: update ns2cycle calculation method For the original method change from plus 1 to minus 1, this way make the default timing like tCS become 0 after calculation, although we set the timing as 0xa... Change the method to no plus and minus, and make the result closer to what the timing specified in the NAND chip spec. Signed-off-by: Lei Wen --- drivers/mtd/nand/pxa3xx_nand.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index e02fa4f..4d89f37 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -363,7 +363,7 @@ static struct pxa3xx_nand_flash *builtin_flash_types[] = { #define tAR_NDTR1(r) (((r) >> 0) & 0xf) /* convert nano-seconds to nand flash controller clock cycles */ -#define ns2cycle(ns, clk) (int)(((ns) * (clk / 1000000) / 1000) - 1) +#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) /* convert nand flash controller clock cycles to nano-seconds */ #define cycle2ns(c, clk) ((((c) + 1) * 1000000 + clk / 500) / (clk / 1000)) -- 1.7.0.4