From patchwork Tue Jul 27 19:42:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 60042 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 1C16BB70B4 for ; Wed, 28 Jul 2010 05:43:43 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1Odq2e-0002zH-SZ; Tue, 27 Jul 2010 19:42:20 +0000 Received: from mms1.broadcom.com ([216.31.210.17]) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1Odq2c-0002us-6A for linux-mtd@lists.infradead.org; Tue, 27 Jul 2010 19:42:19 +0000 Received: from [10.9.200.133] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Tue, 27 Jul 2010 12:42:06 -0700 X-Server-Uuid: 02CED230-5797-4B57-9875-D5D2FEE4708A Received: from mail-irva-12.broadcom.com (10.11.16.101) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Tue, 27 Jul 2010 12:43:26 -0700 Received: from [10.12.160.50] (ld-irv-0074.broadcom.com [10.12.160.50]) by mail-irva-12.broadcom.com (Postfix) with ESMTP id B769369CA8; Tue, 27 Jul 2010 12:42:05 -0700 (PDT) Message-ID: <4C4F3691.9020505@broadcom.com> Date: Tue, 27 Jul 2010 12:42:09 -0700 From: "Brian Norris" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.11) Gecko/20100713 Thunderbird/3.0.6 MIME-Version: 1.0 To: "linux-mtd@lists.infradead.org" Subject: [PATCH v2] mtd/nand: Support Micron chips, pagesize >= 4KB References: <4C4DEA3D.5070208@broadcom.com> In-Reply-To: <4C4DEA3D.5070208@broadcom.com> X-WSS-ID: 6051E90437O37471880-01-01 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100727_154218_463762_87E3CB2D X-CRM114-Status: GOOD ( 14.98 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Thomas Gleixner , David Woodhouse , Maxim Levitsky , Brian Norris , Artem Bityutskiy X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org I found some newer Micron parts that introduce an 8K page size, and so need a modification on the algorithm. Here's the updated list and a revision to my patch. Part ID String Block Page OOB MT29F16G08ABABA 2C 48 00 26 89 00 00 512K 4K 224 MT29F16G08CBABA 2C 48 04 46 85 00 00 1024K 4K 224 MT29F16G08MAA 2C D5 94 3E 74 00 00 512K 4K 218 MT29F32G08CBACA 2C 68 04 4A A9 00 00 1024K 4K 224 MT29F64G08CBAAA 2C 88 04 4B A9 00 00 2048K 8K 448 MT29F256G08CJAAA 2C A8 05 CB A9 00 00 2048K 8K 448 Signed-off-by: Brian Norris --- drivers/mtd/nand/nand_base.c | 37 ++++++++++++++++++++++++++++--------- drivers/mtd/nand/nand_ids.c | 10 ++++++++++ 2 files changed, 38 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 4a7b864..a9216af 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2846,6 +2846,9 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) * New style (6 byte ID): Samsung K9GAG08U0D (p.40) + * Micron (5 byte ID): Micron MT29F16G08MAA (p.24) + * Note: Micron rule is based on heuristics for + * newer chips * * Check for wraparound + Samsung ID + nonzero 6th byte * to decide what to do. @@ -2867,15 +2870,31 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); extid >>= 2; - /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * - (mtd->writesize >> 9); - extid >>= 2; - /* Calc blocksize. Blocksize is multiples of 64KiB */ - mtd->erasesize = (64 * 1024) << (extid & 0x03); - extid >>= 2; - /* Get buswidth information */ - busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + /* Check for 5 byte ID + Micron + read more 0x00 */ + if (id_data[0] == NAND_MFR_MICRON && id_data[4] != 0x00 + && mtd->writesize >= 4096 + && id_data[5] == 0x00 + && id_data[6] == 0x00) { + /* OOB is 218B/224B per 4KiB pagesize */ + mtd->oobsize = ((extid & 0x03) == 0x03 ? 218 : + 224) << (mtd->writesize >> 13); + extid >>= 3; + /* Blocksize is multiple of 64KiB */ + mtd->erasesize = mtd->writesize << + (extid & 0x03) << 6; + /* All Micron have busw x8? */ + busw = 0; + } else { + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x01)) * + (mtd->writesize >> 9); + extid >>= 2; + /* Calc blocksize (multiples of 64KiB) */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + } } } else { /* diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 89907ed..4f6e59a 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -107,9 +107,19 @@ struct nand_flash_dev nand_flash_ids[] = { /* 16 Gigabit */ {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS}, {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS}, + {"NAND 2GiB 3,3V 8-bit", 0x48, 0, 2048, 0, LP_OPTIONS}, {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16}, + /* 32 Gigabit */ + {"NAND 4GiB 3,3V 8-bit", 0x68, 0, 4096, 0, LP_OPTIONS}, + + /* 64 Gigabit */ + {"NAND 8GiB 3,3V 8-bit", 0x88, 0, 8192, 0, LP_OPTIONS}, + + /* 256 Gigabit */ + {"NAND 32GiB 3,3V 8-bit", 0xA8, 0, 32768, 0, LP_OPTIONS}, + /* * Renesas AND 1 Gigabit. Those chips do not support extended id and * have a strange page/block layout ! The chosen minimum erasesize is