From patchwork Mon Jul 26 20:04:13 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Norris X-Patchwork-Id: 59946 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [18.85.46.34]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 74C9CB6F07 for ; Tue, 27 Jul 2010 06:06:00 +1000 (EST) Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OdTub-0007oy-RV; Mon, 26 Jul 2010 20:04:33 +0000 Received: from mms3.broadcom.com ([216.31.210.19]) by bombadil.infradead.org with esmtp (Exim 4.72 #1 (Red Hat Linux)) id 1OdTuW-0007iH-F1 for linux-mtd@lists.infradead.org; Mon, 26 Jul 2010 20:04:32 +0000 Received: from [10.9.200.133] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Mon, 26 Jul 2010 13:04:14 -0700 X-Server-Uuid: B55A25B1-5D7D-41F8-BC53-C57E7AD3C201 Received: from mail-irva-12.broadcom.com (10.11.16.101) by IRVEXCHHUB02.corp.ad.broadcom.com (10.9.200.133) with Microsoft SMTP Server id 8.2.247.2; Mon, 26 Jul 2010 13:05:34 -0700 Received: from [10.12.160.50] (ld-irv-0074.broadcom.com [10.12.160.50]) by mail-irva-12.broadcom.com (Postfix) with ESMTP id 5FB6569CA9; Mon, 26 Jul 2010 13:04:14 -0700 (PDT) Message-ID: <4C4DEA3D.5070208@broadcom.com> Date: Mon, 26 Jul 2010 13:04:13 -0700 From: "Brian Norris" User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.10) Gecko/20100528 Thunderbird/3.0.5 MIME-Version: 1.0 To: "linux-mtd@lists.infradead.org" Subject: [PATCH] mtd/nand: Support Micron chips, 4KB page X-WSS-ID: 605335B43KC52238160-01-01 X-CRM114-Version: 20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20100726_160429_328365_F398AF38 X-CRM114-Status: GOOD ( 18.84 ) X-Spam-Score: -0.0 (/) X-Spam-Report: SpamAssassin version 3.3.1 on bombadil.infradead.org summary: Content analysis details: (-0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain Cc: Thomas Gleixner , David Woodhouse , Maxim Levitsky , Brian Norris , Artem Bityutskiy X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.12 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-mtd-bounces@lists.infradead.org Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The following parts exhibit some interesting patterns in their ID strings. Their ID strings are not fully compatible with the current nand_base.c detection algorithm. In order to detect them properly, I have taken the liberty to develop a heuristic algorithm. None of these chips have a *good* detection pattern listed in their datasheets, although MT29F16G08MAA has a table on p.24 of its data sheet (not included here). Part ID String Block Page OOB MT29F16G08ABABA 2C 48 00 26 89 00 00 512K 4K 224 MT29F16G08CBABA 2C 48 04 46 85 00 00 1024K 4K 224 MT29F16G08MAA 2C D5 94 3E 74 00 00 512K 4K 218 I have attached a table logging most of the relevant data for the many chips I have researched. The three chips are highlighted red, although there are variants of the chips listed as well. I believe this patch should correctly identify all the 5-byte ID Micron chips. And before the question is asked: I realize that these chips support ONFI, so that should be the primary means by which to identify them, but I would still like to be able to detect these properly without ONFI if necessary, especially considering some of the older NAND controllers we still use do not support reading ONFI data. Feedback on my logic is appreciated. Signed-off-by: Brian Norris --- drivers/mtd/nand/nand_base.c | 34 +++++++++++++++++++++++++--------- drivers/mtd/nand/nand_ids.c | 1 + 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 4a7b864..1ca230d 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2846,6 +2846,9 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, * Field definitions are in the following datasheets: * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32) * New style (6 byte ID): Samsung K9GAG08U0D (p.40) + * Micron (5 byte ID): Micron MT29F16G08MAA (p.24) + * Note: Micron rule is based on heuristics for + * newer chips * * Check for wraparound + Samsung ID + nonzero 6th byte * to decide what to do. @@ -2867,15 +2870,28 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, /* Calc pagesize */ mtd->writesize = 1024 << (extid & 0x03); extid >>= 2; - /* Calc oobsize */ - mtd->oobsize = (8 << (extid & 0x01)) * - (mtd->writesize >> 9); - extid >>= 2; - /* Calc blocksize. Blocksize is multiples of 64KiB */ - mtd->erasesize = (64 * 1024) << (extid & 0x03); - extid >>= 2; - /* Get buswidth information */ - busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + /* Check for 5 byte ID + Micron + read more 0x00 */ + if (id_data[0] == NAND_MFR_MICRON && id_data[4] != 0x00 + && mtd->writesize >= 4096 + && id_data[5] == 0x00 + && id_data[6] == 0x00) { + mtd->oobsize = ((extid & 0x03) == 0x03) ? 218 + : 224; + extid >>= 3; + mtd->erasesize = (256 * 1024) << (extid & 0x03); + /* All Micron have busw x8? */ + busw = 0; + } else { + /* Calc oobsize */ + mtd->oobsize = (8 << (extid & 0x01)) * + (mtd->writesize >> 9); + extid >>= 2; + /* Calc blocksize (multiples of 64KiB) */ + mtd->erasesize = (64 * 1024) << (extid & 0x03); + extid >>= 2; + /* Get buswidth information */ + busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0; + } } } else { /* diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 89907ed..25f6be2 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -107,6 +107,7 @@ struct nand_flash_dev nand_flash_ids[] = { /* 16 Gigabit */ {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS}, {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS}, + {"NAND 2GiB 3,3V 8-bit", 0x48, 0, 2048, 0, LP_OPTIONS}, {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16}, {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},