| Message ID | 20231014120436.1515339-1-niravkumar.l.rabara@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] dt-bindings: mtd: cadence: convert cadence-nand-controller.txt to yaml | expand |
On Sat, Oct 14, 2023 at 08:04:36PM +0800, niravkumar.l.rabara@intel.com wrote: > From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > > Convert cadence-nand-controller.txt to yaml format. > Update cadence-nand-controller.txt to cdns,hp-nfc.yaml in MAINTAINER file. > > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> This seems okay to me, thanks. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Conor. > --- > > Changes in v3: > - Changed file name to cdns,hp-nfc.yaml to match with compatible. > - Update description, fixed alignment, and used defines for interrupt > flag as per review comments in v2. > > Changes in v2: > - Update name cadence-nand-controller.txt to cadence,nand.yaml in MAINTAINER > file to resolve the warning. > > .../bindings/mtd/cadence-nand-controller.txt | 53 ------------- > .../devicetree/bindings/mtd/cdns,hp-nfc.yaml | 75 +++++++++++++++++++ > MAINTAINERS | 2 +- > 3 files changed, 76 insertions(+), 54 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > create mode 100644 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml > > diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > deleted file mode 100644 > index d2eada5044b2..000000000000 > --- a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > +++ /dev/null > @@ -1,53 +0,0 @@ > -* Cadence NAND controller > - > -Required properties: > - - compatible : "cdns,hp-nfc" > - - reg : Contains two entries, each of which is a tuple consisting of a > - physical address and length. The first entry is the address and > - length of the controller register set. The second entry is the > - address and length of the Slave DMA data port. > - - reg-names: should contain "reg" and "sdma" > - - #address-cells: should be 1. The cell encodes the chip select connection. > - - #size-cells : should be 0. > - - interrupts : The interrupt number. > - - clocks: phandle of the controller core clock (nf_clk). > - > -Optional properties: > - - dmas: shall reference DMA channel associated to the NAND controller > - - cdns,board-delay-ps : Estimated Board delay. The value includes the total > - round trip delay for the signals and is used for deciding on values > - associated with data read capture. The example formula for SDR mode is > - the following: > - board delay = RE#PAD delay + PCB trace to device + PCB trace from device > - + DQ PAD delay > - > -Child nodes represent the available NAND chips. > - > -Required properties of NAND chips: > - - reg: shall contain the native Chip Select ids from 0 to max supported by > - the cadence nand flash controller > - > -See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on > -generic bindings. > - > -Example: > - > -nand_controller: nand-controller@60000000 { > - compatible = "cdns,hp-nfc"; > - #address-cells = <1>; > - #size-cells = <0>; > - reg = <0x60000000 0x10000>, <0x80000000 0x10000>; > - reg-names = "reg", "sdma"; > - clocks = <&nf_clk>; > - cdns,board-delay-ps = <4830>; > - interrupts = <2 0>; > - nand@0 { > - reg = <0>; > - label = "nand-1"; > - }; > - nand@1 { > - reg = <1>; > - label = "nand-2"; > - }; > - > -}; > diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml > new file mode 100644 > index 000000000000..402930995bd7 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Cadence NAND controller > + > +maintainers: > + - Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > + > +allOf: > + - $ref: nand-controller.yaml > + > +properties: > + compatible: > + items: > + - const: cdns,hp-nfc > + > + reg: > + items: > + - description: Controller register set > + - description: Slave DMA data port register set > + > + reg-names: > + items: > + - const: reg > + - const: sdma > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + dmas: > + maxItems: 1 > + > + cdns,board-delay-ps: > + description: | > + Estimated Board delay. The value includes the total round trip > + delay for the signals and is used for deciding on values associated > + with data read capture. The example formula for SDR mode is the > + following. > + board delay = RE#PAD delay + PCB trace to device + PCB trace from device > + + DQ PAD delay > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - clocks > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + nand-controller@10b80000 { > + compatible = "cdns,hp-nfc"; > + reg = <0x10b80000 0x10000>, > + <0x10840000 0x10000>; > + reg-names = "reg", "sdma"; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&nf_clk>; > + cdns,board-delay-ps = <4830>; > + > + nand@0 { > + reg = <0>; > + }; > + }; > diff --git a/MAINTAINERS b/MAINTAINERS > index 90f13281d297..226efb6352e2 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -4474,7 +4474,7 @@ F: drivers/media/platform/cadence/cdns-csi2* > CADENCE NAND DRIVER > L: linux-mtd@lists.infradead.org > S: Orphan > -F: Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt > +F: Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml > F: drivers/mtd/nand/raw/cadence-nand-controller.c > > CADENCE USB3 DRD IP DRIVER > -- > 2.25.1 > >
On 14/10/2023 14:04, niravkumar.l.rabara@intel.com wrote: > From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > > Convert cadence-nand-controller.txt to yaml format. > Update cadence-nand-controller.txt to cdns,hp-nfc.yaml in MAINTAINER file. > > Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> > --- ... > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + nand-controller@10b80000 { > + compatible = "cdns,hp-nfc"; > + reg = <0x10b80000 0x10000>, > + <0x10840000 0x10000>; > + reg-names = "reg", "sdma"; > + #address-cells = <1>; > + #size-cells = <0>; > + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&nf_clk>; > + cdns,board-delay-ps = <4830>; > + > + nand@0 { > + reg = <0>; > + }; > + }; You still have wrong indentation here. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt b/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt deleted file mode 100644 index d2eada5044b2..000000000000 --- a/Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt +++ /dev/null @@ -1,53 +0,0 @@ -* Cadence NAND controller - -Required properties: - - compatible : "cdns,hp-nfc" - - reg : Contains two entries, each of which is a tuple consisting of a - physical address and length. The first entry is the address and - length of the controller register set. The second entry is the - address and length of the Slave DMA data port. - - reg-names: should contain "reg" and "sdma" - - #address-cells: should be 1. The cell encodes the chip select connection. - - #size-cells : should be 0. - - interrupts : The interrupt number. - - clocks: phandle of the controller core clock (nf_clk). - -Optional properties: - - dmas: shall reference DMA channel associated to the NAND controller - - cdns,board-delay-ps : Estimated Board delay. The value includes the total - round trip delay for the signals and is used for deciding on values - associated with data read capture. The example formula for SDR mode is - the following: - board delay = RE#PAD delay + PCB trace to device + PCB trace from device - + DQ PAD delay - -Child nodes represent the available NAND chips. - -Required properties of NAND chips: - - reg: shall contain the native Chip Select ids from 0 to max supported by - the cadence nand flash controller - -See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on -generic bindings. - -Example: - -nand_controller: nand-controller@60000000 { - compatible = "cdns,hp-nfc"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x60000000 0x10000>, <0x80000000 0x10000>; - reg-names = "reg", "sdma"; - clocks = <&nf_clk>; - cdns,board-delay-ps = <4830>; - interrupts = <2 0>; - nand@0 { - reg = <0>; - label = "nand-1"; - }; - nand@1 { - reg = <1>; - label = "nand-2"; - }; - -}; diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml new file mode 100644 index 000000000000..402930995bd7 --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence NAND controller + +maintainers: + - Niravkumar L Rabara <niravkumar.l.rabara@intel.com> + +allOf: + - $ref: nand-controller.yaml + +properties: + compatible: + items: + - const: cdns,hp-nfc + + reg: + items: + - description: Controller register set + - description: Slave DMA data port register set + + reg-names: + items: + - const: reg + - const: sdma + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + dmas: + maxItems: 1 + + cdns,board-delay-ps: + description: | + Estimated Board delay. The value includes the total round trip + delay for the signals and is used for deciding on values associated + with data read capture. The example formula for SDR mode is the + following. + board delay = RE#PAD delay + PCB trace to device + PCB trace from device + + DQ PAD delay + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + nand-controller@10b80000 { + compatible = "cdns,hp-nfc"; + reg = <0x10b80000 0x10000>, + <0x10840000 0x10000>; + reg-names = "reg", "sdma"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nf_clk>; + cdns,board-delay-ps = <4830>; + + nand@0 { + reg = <0>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..226efb6352e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4474,7 +4474,7 @@ F: drivers/media/platform/cadence/cdns-csi2* CADENCE NAND DRIVER L: linux-mtd@lists.infradead.org S: Orphan -F: Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt +F: Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml F: drivers/mtd/nand/raw/cadence-nand-controller.c CADENCE USB3 DRD IP DRIVER