| Message ID | 20230818145101.23825-2-quic_mdalam@quicinc.com |
|---|---|
| State | New |
| Headers | show |
| Series | mtd: rawnand: qcom: Fixes for exec_op | expand |
Hi Md, quic_mdalam@quicinc.com wrote on Fri, 18 Aug 2023 20:20:59 +0530: > For parameter page read upper layer is passing len > as 256 bytes and if we try to configure 256 bytes > size in read loaction register then subsequent bam > transaction is getting timed out for 4K nand devices. > So update this length as one step size if its > less than NANDC_STEP_SIZE. > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> I'm fine with patches 2 and 3 and will take them. But this one does not seem legitimate. I don't like it. Are you sure the ECC engine was not enabled when it timed out? Default should be having the ECC disabled and it should just get enabled when you need it. There is no reason why, specifically on NAND devices, it would not be possible to read 256 bytes. > --- > drivers/mtd/nand/raw/qcom_nandc.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c > index d4ba0d04c970..413e214c8e87 100644 > --- a/drivers/mtd/nand/raw/qcom_nandc.c > +++ b/drivers/mtd/nand/raw/qcom_nandc.c > @@ -2885,6 +2885,9 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ > op_id = q_op.data_instr_idx; > len = nand_subop_get_data_len(subop, op_id); > > + if (len < NANDC_STEP_SIZE) > + len = NANDC_STEP_SIZE; > + > nandc_set_read_loc(chip, 0, 0, 0, len, 1); > > if (!nandc->props->qpic_v2) { Thanks, Miquèl
On 8/19/2023 1:29 AM, Miquel Raynal wrote: > Hi Md, > > quic_mdalam@quicinc.com wrote on Fri, 18 Aug 2023 20:20:59 +0530: > >> For parameter page read upper layer is passing len >> as 256 bytes and if we try to configure 256 bytes >> size in read loaction register then subsequent bam >> transaction is getting timed out for 4K nand devices. >> So update this length as one step size if its >> less than NANDC_STEP_SIZE. >> >> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> >> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> > > I'm fine with patches 2 and 3 and will take them. But this one does not > seem legitimate. I don't like it. Are you sure the ECC engine was not > enabled when it timed out? Default should be having the ECC disabled > and it should just get enabled when you need it. There is no reason > why, specifically on NAND devices, it would not be possible to read 256 > bytes. > Yes default ECC engine is disabled only. When length was 512 bytes for parameter page read it was causing BAM timeout error on SDX65, but it was working fine on IPQ807x. We will drop this patch for now. Let me check on SDX65 and try to fix all the error. >> --- >> drivers/mtd/nand/raw/qcom_nandc.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c >> index d4ba0d04c970..413e214c8e87 100644 >> --- a/drivers/mtd/nand/raw/qcom_nandc.c >> +++ b/drivers/mtd/nand/raw/qcom_nandc.c >> @@ -2885,6 +2885,9 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ >> op_id = q_op.data_instr_idx; >> len = nand_subop_get_data_len(subop, op_id); >> >> + if (len < NANDC_STEP_SIZE) >> + len = NANDC_STEP_SIZE; >> + >> nandc_set_read_loc(chip, 0, 0, 0, len, 1); >> >> if (!nandc->props->qpic_v2) { > > > Thanks, > Miquèl
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index d4ba0d04c970..413e214c8e87 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -2885,6 +2885,9 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_ op_id = q_op.data_instr_idx; len = nand_subop_get_data_len(subop, op_id); + if (len < NANDC_STEP_SIZE) + len = NANDC_STEP_SIZE; + nandc_set_read_loc(chip, 0, 0, 0, len, 1); if (!nandc->props->qpic_v2) {