| Message ID | 20230703035044.2063303-3-chris.packham@alliedtelesis.co.nz |
|---|---|
| State | New |
| Delegated to: | Miquel Raynal |
| Headers | show |
| Series | mtd: rawnand: marvell: add support for AC5 SoC | expand |
Chris Packham <chris.packham@alliedtelesis.co.nz> writes: > The AC5/AC5X SoC has a NAND flash controller (NFC). Add this to > the base SoC dtsi file as a disabled node. The NFC integration > on the AC5/AC5X only supports SDR timing modes up to 3 so requires a > dedicated compatible property so this limitation can be enforced. > > Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Now that binding and code has beeen applied I can apply this one on mvebu/dt64 Thanks, Gregory > --- > > Notes: > Changes in v3: > - Use correct clock for NFC > Changes in v2: > - New. > > arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > index c9ce1010c415..c64aaf51deb8 100644 > --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi > @@ -297,6 +297,16 @@ spi1: spi@805a8000 { > status = "disabled"; > }; > > + nand: nand-controller@805b0000 { > + compatible = "marvell,ac5-nand-controller"; > + reg = <0x0 0x805b0000 0x0 0x00000054>; > + #address-cells = <0x1>; > + #size-cells = <0x0>; > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&nand_clock>; > + status = "disabled"; > + }; > + > gic: interrupt-controller@80600000 { > compatible = "arm,gic-v3"; > #interrupt-cells = <3>; > @@ -319,5 +329,11 @@ spi_clock: spi-clock { > #clock-cells = <0>; > clock-frequency = <200000000>; > }; > + > + nand_clock: nand-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <400000000>; > + }; > }; > }; > -- > 2.41.0 >
diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index c9ce1010c415..c64aaf51deb8 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -297,6 +297,16 @@ spi1: spi@805a8000 { status = "disabled"; }; + nand: nand-controller@805b0000 { + compatible = "marvell,ac5-nand-controller"; + reg = <0x0 0x805b0000 0x0 0x00000054>; + #address-cells = <0x1>; + #size-cells = <0x0>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&nand_clock>; + status = "disabled"; + }; + gic: interrupt-controller@80600000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; @@ -319,5 +329,11 @@ spi_clock: spi-clock { #clock-cells = <0>; clock-frequency = <200000000>; }; + + nand_clock: nand-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; }; };
The AC5/AC5X SoC has a NAND flash controller (NFC). Add this to the base SoC dtsi file as a disabled node. The NFC integration on the AC5/AC5X only supports SDR timing modes up to 3 so requires a dedicated compatible property so this limitation can be enforced. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> --- Notes: Changes in v3: - Use correct clock for NFC Changes in v2: - New. arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)