diff mbox series

Linux: SPI: add Gigadevice part #

Message ID 20221204080000.4100-1-vlim@gigadevice.com
State Changes Requested
Headers show
Series Linux: SPI: add Gigadevice part # | expand

Commit Message

Victor Lim Dec. 4, 2022, 8 a.m. UTC 
Edited gigadevice.c

Signed-off-by: Victor Lim <vlim@gigadevice.com>
---
 drivers/mtd/spi-nor/gigadevice.c | 115 ++++++++++++++++++++++++-------
 1 file changed, 91 insertions(+), 24 deletions(-)

Comments

Michael Walle Dec. 5, 2022, 8:22 a.m. UTC | #1 
Hi,

Am 2022-12-04 09:00, schrieb Victor Lim:
> Edited gigadevice.c

Please have a look at
https://www.kernel.org/doc/html/latest/process/submitting-patches.html

-michael
Michael Walle Dec. 6, 2022, 8:17 a.m. UTC | #2 
Hi,

Am 2022-12-06 02:27, schrieb Vlim:
>  I will redo the patch following this doc.
>  At the meantime, can you point out a few mistakes that I am making so
> that I can correct it in the next submit.

I really don't know what you want to achieve with this patch. It
has a bunch of renames. So what is the intention of the renames?

-michael
Miquel Raynal Dec. 6, 2022, 8:18 a.m. UTC | #3 
Hi Vlim,

vlim@gigadevice.com wrote on Tue, 6 Dec 2022 01:27:13 +0000:

> Hi, Michael,
> 
> I will redo the patch following this doc.
> At the meantime, can you point out a few mistakes that I am making so that I can correct it in the next submit.

Here are a few:
- The title is wrong (git log --oneline <file> for hints)
- The commit log is useless
- Don't make unrelated changes in your commit, one change == one commit
- Don't change how the code looks like for no reason or justification

And please avoid top posting when answering.

Good luck!

Thanks,
Miquèl

> 
> ________________________________
> From: Michael Walle <michael@walle.cc>
> Sent: Monday, December 5, 2022 00:22
> To: Victor Lim <victorswlim@gmail.com>
> Cc: tudor.ambarus@microchip.com <tudor.ambarus@microchip.com>; p.yadav@ti.com <p.yadav@ti.com>; miquel.raynal@bootlin.com <miquel.raynal@bootlin.com>; richard@nod.at <richard@nod.at>; vigneshr@ti.com <vigneshr@ti.com>; linux-mtd@lists.infradead.org <linux-mtd@lists.infradead.org>; linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>; vikhyat.goyal@amd.com <vikhyat.goyal@amd.com>; amit.kumar-mahapatra@amd.com <amit.kumar-mahapatra@amd.com>; alejandro.carmona@amd.com <alejandro.carmona@amd.com>; Vlim <vlim@gigadevice.com>
> Subject: Re: [PATCH] Linux: SPI: add Gigadevice part #
> 
> [You don't often get email from michael@walle.cc. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> 此为外部邮件，谨防钓鱼邮件，请注意邮件是否涉及敏感信息
> 
> This is an external email, beware of phishing emails. Please pay close attention to whether the email contains sensitive information
> 
> 
> Hi,
> 
> Am 2022-12-04 09:00, schrieb Victor Lim:
> > Edited gigadevice.c  
> 
> Please have a look at
> https://www.kernel.org/doc/html/latest/process/submitting-patches.html
> 
> -michael
Miquel Raynal Dec. 6, 2022, 8:44 a.m. UTC | #4 
Hi Vlim,

vlim@gigadevice.com wrote on Tue, 6 Dec 2022 08:27:02 +0000:

> Hi, Michael, Miguel,
> 
> This is to add many part numbers to the gigadevice.c so that Linux would recognize these part numbers during booting up.
> 
> Can I make one patch for all these part numbers? Only one file is affected.

Have a look at the diff, if it is not obvious that you are trying to
add a couple of part numbers, then it makes your patch wrongly written.

Thanks,
Miquèl
Frieder Schrempf Dec. 6, 2022, 11:37 a.m. UTC | #5 
On 06.12.22 09:18, Miquel Raynal wrote:
> Hi Vlim,
> 
> vlim@gigadevice.com wrote on Tue, 6 Dec 2022 01:27:13 +0000:
> 
>> Hi, Michael,
>>
>> I will redo the patch following this doc.
>> At the meantime, can you point out a few mistakes that I am making so that I can correct it in the next submit.
> 
> Here are a few:
> - The title is wrong (git log --oneline <file> for hints)
> - The commit log is useless
> - Don't make unrelated changes in your commit, one change == one commit
> - Don't change how the code looks like for no reason or justification
> 
> And please avoid top posting when answering.

Here are some more:

* sending (almost) the same wrong patch again ignoring feedback from
maintainers
* not using version prefixes in your subject line (PATCH v2: ...)
* not adding a changelog to your patch
* keeping your replies off the mailing list (probably your @gigadevice
address is not subscribed!?)
Frieder Schrempf Dec. 6, 2022, 11:44 a.m. UTC | #6 
On 06.12.22 12:37, Frieder Schrempf wrote:
> On 06.12.22 09:18, Miquel Raynal wrote:
>> Hi Vlim,
>>
>> vlim@gigadevice.com wrote on Tue, 6 Dec 2022 01:27:13 +0000:
>>
>>> Hi, Michael,
>>>
>>> I will redo the patch following this doc.
>>> At the meantime, can you point out a few mistakes that I am making so that I can correct it in the next submit.
>>
>> Here are a few:
>> - The title is wrong (git log --oneline <file> for hints)
>> - The commit log is useless
>> - Don't make unrelated changes in your commit, one change == one commit
>> - Don't change how the code looks like for no reason or justification
>>
>> And please avoid top posting when answering.
> 
> Here are some more:
> 
> * sending (almost) the same wrong patch again ignoring feedback from
> maintainers
> * not using version prefixes in your subject line (PATCH v2: ...)

The example should be like this of course: [PATCH v2] ...

> * not adding a changelog to your patch
> * keeping your replies off the mailing list (probably your @gigadevice
> address is not subscribed!?)
diff mbox series

Patch

diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c
index 66c2e75023fc..9309e57407e6 100644
--- a/drivers/mtd/spi-nor/gigadevice.c
+++ b/drivers/mtd/spi-nor/gigadevice.c
@@ -154,38 +154,105 @@  static struct spi_nor_fixups gd25q256_fixups = {
 };
 
 static const struct flash_info gigadevice_parts[] = {
-	{ "gd25q16", INFO(0xc84015, 0, 64 * 1024,  32,
-			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
-	{ "gd25q32", INFO(0xc84016, 0, 64 * 1024,  64,
-			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
-	{ "gd25lq32", INFO(0xc86016, 0, 64 * 1024, 64,
-			   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
-	{ "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,
-			  SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			  SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
-	{ "gd25lq64c", INFO(0xc86017, 0, 64 * 1024, 128,
-			    SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			    SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
-	{ "gd25lq128d", INFO(0xc86018, 0, 64 * 1024, 256,
-			     SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			     SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
-	{ "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,
-			   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
-			   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },
-	{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
+/* GigaDevice - GD25Q or B series  */
+	{"gd25q16", INFO(0xc84015, 0, 64 * 1024,  32,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |	SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},
+	{"gd25q32", INFO(0xc84016, 0, 64 * 1024,  64,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |	SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},
+	{"gd25q64", INFO(0xc84017, 0, 64 * 1024, 128,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |	SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},
+	{"gd25q128", INFO(0xc84018, 0, 64 * 1024, 256,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ	|	SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)},
+		{ "gd25q256", INFO(0xc84019, 0, 64 * 1024, 512,
 			   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
 			   SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
 			   SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6)
-		.fixups = &gd25q256_fixups },
+	.fixups = &gd25q256_fixups },
+	{"gd25b series 512Mbit", INFO(0xc8471A, 0, 64 * 1024, 1024,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55b series 1Gbit", INFO(0xc8471B, 0, 64 * 1024, 2048,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55b series 2Gbit", INFO(0xc8471C, 0, 64 * 1024, 4096,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+/* GigaDevice - GD25F series */
+	{"gd25f series 64Mbit", INFO(0xc84317, 0, 64 * 1024, 128,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+	{"gd25f series 128Mbit", INFO(0xc84318, 0, 64 * 1024, 256,	SECT_4K	|
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+	{"gd25f series 256Mbit", INFO(0xc84319, 0, 64 * 1024, 512,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55f series 512Mbit", INFO(0xc8431A, 0, 64 * 1024, 1024,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+/* GigaDevice - GD25T series */
+	{"gd25t series 512Mbit", INFO(0xc8461A, 0, 64 * 1024, 1024,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55t series 1Gbit", INFO(0xc8461B, 0, 64 * 1024, 2048,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55t02ge", INFO(0xc8461C, 0, 64 * 1024, 4096,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+/* GigaDevice - GD25X series */
+	{"gd25x series 512Mbit", INFO(0xc8481A, 0, 64 * 1024, 1024,	SECT_4K |
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+	{"gd55x series 1Gbit", INFO(0xc8481B, 0, 64 * 1024, 2048,	SECT_4K |
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+	{"gd55x series 2Gbit", INFO(0xc8481C, 0, 64 * 1024, 4096,	SECT_4K |
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+/* GigaDevice - GD25LB series */
+	{"gd25lb series 16Mbit", INFO(0xc86015, 0, 64 * 1024, 32,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+	{"gd25lb series 32Mbit", INFO(0xc86016, 0, 64 * 1024, 64,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)	},
+	{"gd25lb series 64Mbit", INFO(0xc86017, 0, 64 * 1024, 128,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)	},
+	{"gd25lb series 128Mbit", INFO(0xc86018, 0, 64 * 1024, 256,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+	{"gd25lb series 256Mbit", INFO(0xc86019, 0, 64 * 1024, 512,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd25lb series 256Mbit", INFO(0xc86719, 0, 64 * 1024, 512,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd25lb series 512Mbit", INFO(0xc8671A, 0, 64 * 1024, 1024,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55lb series 1Gbit", INFO(0xc8671B, 0, 64 * 1024, 2048,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55lb series 2Gbit", INFO(0xc8671C, 0, 64 * 1024, 4096,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+/* GigaDevice - GD25LF series */
+	{"gd25lf series 8Mbit", INFO(0xc86314, 0, 64 * 1024, 16,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+	{"gd25lf series 16Mbit", INFO(0xc86315, 0, 64 * 1024, 32,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+	{"gd25lf series 32Mbit", INFO(0xc86316, 0, 64 * 1024, 64,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)	},
+	{"gd25lf series 64Mbit", INFO(0xc86317, 0, 64 * 1024, 128,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)	},
+	{"gd25lf series 128Mbit", INFO(0xc86318, 0, 64 * 1024, 256,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)	},
+	{"gd25lf series 256Mbit", INFO(0xc86319, 0, 64 * 1024, 512,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd25lf series 512Mbit", INFO(0xc8631A, 0, 64 * 1024, 1024,	SECT_4K |
+	SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+/* GigaDevice - GD25LT series */
+	{"gd25lt256e", INFO(0xc86619, 0, 64 * 1024, 512,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd25lt512me", INFO(0xc8661A, 0, 64 * 1024, 1024,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55lt01ge", INFO(0xc8661B, 0, 64 * 1024, 2048,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+	{"gd55lt02ge", INFO(0xc8661C, 0, 64 * 1024, 4096,	SECT_4K |
+	SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+/* GigaDevice - GD25LX series */
 	{ "gd25lx256e",  INFO(0xc86819, 0, 64 * 1024, 512,
 			      SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
 			      SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ |
 			      SPI_NOR_OCTAL_DTR_PP |
 			      SPI_NOR_IO_MODE_EN_VOLATILE)
-		.fixups = &gd25lx256e_fixups },
+			      .fixups = &gd25lx256e_fixups },
+	{"gd25lx series 512Mbit", INFO(0xc8681A, 0, 64 * 1024, 1024,	SECT_4K |
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+	{"gd55lx series 1Gbit", INFO(0xc8681B, 0, 64 * 1024, 2048,	SECT_4K |
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+	{"gd55lx series 2Gbit", INFO(0xc8681C, 0, 64 * 1024, 4096,	SECT_4K |
+	SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
 };
 
 const struct spi_nor_manufacturer spi_nor_gigadevice = {