| Message ID | 20220920184808.44876-2-sudip.mukherjee@sifive.com |
|---|---|
| State | Accepted |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | [v3,1/2] mtd: spi-nor: issi: is25wp256: Init flash based on SFDP | expand |
On Tue, Sep 20, 2022 at 7:48 PM Sudip Mukherjee <sudip.mukherjee@sifive.com> wrote: > > SFDP table of some flash chips do not advertise support of Quad Input > Page Program even though it has support. Use flags and add hardware > cap for these chips. > > Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com> > --- > > Change from v2: SPI_NOR_QUAD_PP added to info->flags instead of > info->fixup_flags. > Link: https://lore.kernel.org/lkml/498c33a8-014f-e542-f143-cba5760fafdd@microchip.com/ > > Results from the tests given by Tudor in the following mail. Test result after this patch: # dd if=/dev/urandom of=./qspi_test bs=1M count=6 6+0 records in 6+0 records out # mtd_debug write /dev/mtd4 0 6291456 qspi_test Copied 6291456 bytes from qspi_test to address 0x00000000 in flash # mtd_debug erase /dev/mtd4 0 6291456 Erased 6291456 bytes from address 0x00000000 in flash # mtd_debug read /dev/mtd4 0 6291456 qspi_read Copied 6291456 bytes from address 0x00000000 in flash to qspi_read # hexdump qspi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0600000 # mtd_debug write /dev/mtd4 0 6291456 qspi_test Copied 6291456 bytes from qspi_test to address 0x00000000 in flash # mtd_debug read /dev/mtd4 0 6291456 qspi_read Copied 6291456 bytes from address 0x00000000 in flash to qspi_read # sha1sum qspi_test qspi_read fefab5ffbc2ca7bed3b45732f2fe6a8139cd6248 qspi_test fefab5ffbc2ca7bed3b45732f2fe6a8139cd6248 qspi_read # cat /sys/bus/spi/devices/spi0.0/spi-nor/partname is25wp256 # cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id 9d7019 # cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer issi # xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 53464450060101ff00060110300000ff9d05010380000002ffffffffffff ffffffffffffffffffffffffffffffffffffe520f9ffffffff0f44eb086b 083b80bbfeffffffffff00ffffff44eb0c200f5210d800ff234ac90082d8 11cecccd68467a757a75f7aed55c4a422cfff030faa9ffffffffffffffff ffffffffffffffff501950169ff9c0648fefffff # md5sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp ba14818b9ec42713f24d94d66bb90ba0 /sys/bus/spi/devices/spi0.0/spi-nor/sfdp
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index f2c64006f8d75..992fb332514d8 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2474,6 +2474,12 @@ static void spi_nor_late_init_params(struct spi_nor *nor) */ if (nor->flags & SNOR_F_HAS_LOCK && !nor->params->locking_ops) spi_nor_init_default_locking_ops(nor); + + if (nor->info->flags & SPI_NOR_QUAD_PP) { + nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; + spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_1_1_4], + SPINOR_OP_PP_1_1_4, SNOR_PROTO_1_1_4); + } } /** diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 85b0cf254e974..c2334fe33e2f9 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -458,6 +458,7 @@ struct spi_nor_fixups { * SPI_NOR_NO_ERASE: no erase command needed. * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. + * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * * @no_sfdp_flags: flags that indicate support that can be discovered via SFDP. * Used when SFDP tables are not defined in the flash. These @@ -507,6 +508,7 @@ struct flash_info { #define SPI_NOR_NO_ERASE BIT(6) #define NO_CHIP_ERASE BIT(7) #define SPI_NOR_NO_FR BIT(8) +#define SPI_NOR_QUAD_PP BIT(9) u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) diff --git a/drivers/mtd/spi-nor/issi.c b/drivers/mtd/spi-nor/issi.c index 8b48459b5054c..014cd9038bedc 100644 --- a/drivers/mtd/spi-nor/issi.c +++ b/drivers/mtd/spi-nor/issi.c @@ -73,6 +73,7 @@ static const struct flash_info issi_nor_parts[] = { { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 512) PARSE_SFDP FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + FLAGS(SPI_NOR_QUAD_PP) .fixups = &is25lp256_fixups }, /* PMC */
SFDP table of some flash chips do not advertise support of Quad Input Page Program even though it has support. Use flags and add hardware cap for these chips. Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com> --- Change from v2: SPI_NOR_QUAD_PP added to info->flags instead of info->fixup_flags. Link: https://lore.kernel.org/lkml/498c33a8-014f-e542-f143-cba5760fafdd@microchip.com/ Results from the tests given by Tudor in the following mail. drivers/mtd/spi-nor/core.c | 6 ++++++ drivers/mtd/spi-nor/core.h | 2 ++ drivers/mtd/spi-nor/issi.c | 1 + 3 files changed, 9 insertions(+)