| Message ID | 20201126202614.5710-5-michael@walle.cc |
|---|---|
| State | Changes Requested |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | mtd: spi-nor: keep lock bits if they are non-volatile | expand |
On 11/26/20 10:26 PM, Michael Walle wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > These flashes have some weird BP bits mapping which aren't supported in > the current locking code. Just add a simple unlock op to unprotect the > entire flash array which is needed for legacy behavior. > > Signed-off-by: Michael Walle <michael@walle.cc> > --- > changes since v5 > - new patch > > drivers/mtd/spi-nor/atmel.c | 53 +++++++++++++++++++++++++++++++++++-- > drivers/mtd/spi-nor/core.c | 2 +- > drivers/mtd/spi-nor/core.h | 1 + > 3 files changed, 53 insertions(+), 3 deletions(-) > > diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c > index 49d392c6c8bc..fe6a4653823d 100644 > --- a/drivers/mtd/spi-nor/atmel.c > +++ b/drivers/mtd/spi-nor/atmel.c > @@ -8,10 +8,59 @@ > > #include "core.h" > > +/* > + * The Atmel AT25FS010/AT25FS040 parts have some weird configuration for the > + * block protection bits. We don't support them. But legacy behaviour in linux > + * is to unlock the whole flash array on startup. Therefore, we have to support > + * exactly this operation. > + */ > +static int atmel_at25fs_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) > +{ > + return -EOPNOTSUPP; > +} > + > +static int atmel_at25fs_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) > +{ > + /* We only support unlocking the whole flash array */ > + if (ofs || len != nor->params->size) > + return -EINVAL; > + > + /* > + * Write 0x00 to the status register to try to disable the write > + * protection. This will fail if SRWD (the datasheet calls it WPEN) is > + * set. But there is nothing we can do. > + */ can't we do the same as you did in 5/5? + ret = spi_nor_read_sr(nor, nor->bouncebuf); + if (ret) + return ret; + + sr = nor->bouncebuf[0]; + + if (sr & SR_SRWD) { + sr &= ~SR_SRWD; + ret = spi_nor_write_sr_and_check(nor, sr); + if (ret) + return ret; + } If SRWD is set to 1, we first try to set it to 0. If WP# is asserted, we will catch this in spi_nor_write_sr_and_check() > + nor->bouncebuf[0] = 0; > + > + return spi_nor_write_sr(nor, nor->bouncebuf, 1); and then you can use spi_nor_write_sr_and_check here > +} > + > +static int atmel_at25fs_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) > +{ > + return -EOPNOTSUPP; > +} > + > +static const struct spi_nor_locking_ops atmel_at25fs_locking_ops = { > + .lock = atmel_at25fs_lock, > + .unlock = atmel_at25fs_unlock, > + .is_locked = atmel_at25fs_is_locked, > +}; > + > +static void atmel_at25fs_default_init(struct spi_nor *nor) > +{ > + nor->params->locking_ops = &atmel_at25fs_locking_ops; > +} > + > +static const struct spi_nor_fixups atmel_at25fs_fixups = { > + .default_init = atmel_at25fs_default_init, > +}; > + > static const struct flash_info atmel_parts[] = { > /* Atmel -- some are (confusingly) marketed as "DataFlash" */ > - { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K | SPI_NOR_HAS_LOCK) }, > - { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) }, > + { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K | SPI_NOR_HAS_LOCK) > + .fixups = &atmel_at25fs_fixups }, > + { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) > + .fixups = &atmel_at25fs_fixups }, > > { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) }, > { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 5bee7c8da4dc..8c06a28a90de 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -861,7 +861,7 @@ int spi_nor_wait_till_ready(struct spi_nor *nor) > * > * Return: 0 on success, -errno otherwise. > */ > -static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) > +int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) > { > int ret; > > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index 0a775a7b5606..16b350e1d865 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -430,6 +430,7 @@ void spi_nor_unlock_and_unprep(struct spi_nor *nor); > int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); > int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); > int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); > +int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); > > int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr); > ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, > -- > 2.20.1 >
Am 2020-11-28 09:25, schrieb Tudor.Ambarus@microchip.com: > On 11/26/20 10:26 PM, Michael Walle wrote: >> EXTERNAL EMAIL: Do not click links or open attachments unless you know >> the content is safe >> >> These flashes have some weird BP bits mapping which aren't supported >> in >> the current locking code. Just add a simple unlock op to unprotect the >> entire flash array which is needed for legacy behavior. >> >> Signed-off-by: Michael Walle <michael@walle.cc> >> --- >> changes since v5 >> - new patch >> >> drivers/mtd/spi-nor/atmel.c | 53 >> +++++++++++++++++++++++++++++++++++-- >> drivers/mtd/spi-nor/core.c | 2 +- >> drivers/mtd/spi-nor/core.h | 1 + >> 3 files changed, 53 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c >> index 49d392c6c8bc..fe6a4653823d 100644 >> --- a/drivers/mtd/spi-nor/atmel.c >> +++ b/drivers/mtd/spi-nor/atmel.c >> @@ -8,10 +8,59 @@ >> >> #include "core.h" >> >> +/* >> + * The Atmel AT25FS010/AT25FS040 parts have some weird configuration >> for the >> + * block protection bits. We don't support them. But legacy behaviour >> in linux >> + * is to unlock the whole flash array on startup. Therefore, we have >> to support >> + * exactly this operation. >> + */ >> +static int atmel_at25fs_lock(struct spi_nor *nor, loff_t ofs, >> uint64_t len) >> +{ >> + return -EOPNOTSUPP; >> +} >> + >> +static int atmel_at25fs_unlock(struct spi_nor *nor, loff_t ofs, >> uint64_t len) >> +{ >> + /* We only support unlocking the whole flash array */ >> + if (ofs || len != nor->params->size) >> + return -EINVAL; >> + >> + /* >> + * Write 0x00 to the status register to try to disable the >> write >> + * protection. This will fail if SRWD (the datasheet calls it >> WPEN) is >> + * set. But there is nothing we can do. >> + */ > > can't we do the same as you did in 5/5? Sure, but - assuming it is only used for the legacy unlock all operation - the outcome will be the same. It will either keep being locked or all will be unlocked. That being said, I can also change it to the same as the global_unprotect(). I don't have any option on that other than this is simpler. -michael
On 11/30/20 4:16 PM, Michael Walle wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Am 2020-11-28 09:25, schrieb Tudor.Ambarus@microchip.com: >> On 11/26/20 10:26 PM, Michael Walle wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you know >>> the content is safe >>> >>> These flashes have some weird BP bits mapping which aren't supported >>> in >>> the current locking code. Just add a simple unlock op to unprotect the >>> entire flash array which is needed for legacy behavior. >>> >>> Signed-off-by: Michael Walle <michael@walle.cc> >>> --- >>> changes since v5 >>> - new patch >>> >>> drivers/mtd/spi-nor/atmel.c | 53 >>> +++++++++++++++++++++++++++++++++++-- >>> drivers/mtd/spi-nor/core.c | 2 +- >>> drivers/mtd/spi-nor/core.h | 1 + >>> 3 files changed, 53 insertions(+), 3 deletions(-) >>> >>> diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c >>> index 49d392c6c8bc..fe6a4653823d 100644 >>> --- a/drivers/mtd/spi-nor/atmel.c >>> +++ b/drivers/mtd/spi-nor/atmel.c >>> @@ -8,10 +8,59 @@ >>> >>> #include "core.h" >>> >>> +/* >>> + * The Atmel AT25FS010/AT25FS040 parts have some weird configuration >>> for the >>> + * block protection bits. We don't support them. But legacy behaviour >>> in linux >>> + * is to unlock the whole flash array on startup. Therefore, we have >>> to support >>> + * exactly this operation. >>> + */ >>> +static int atmel_at25fs_lock(struct spi_nor *nor, loff_t ofs, >>> uint64_t len) >>> +{ >>> + return -EOPNOTSUPP; >>> +} >>> + >>> +static int atmel_at25fs_unlock(struct spi_nor *nor, loff_t ofs, >>> uint64_t len) >>> +{ >>> + /* We only support unlocking the whole flash array */ >>> + if (ofs || len != nor->params->size) >>> + return -EINVAL; >>> + >>> + /* >>> + * Write 0x00 to the status register to try to disable the >>> write >>> + * protection. This will fail if SRWD (the datasheet calls it >>> WPEN) is >>> + * set. But there is nothing we can do. >>> + */ >> >> can't we do the same as you did in 5/5? > > Sure, but - assuming it is only used for the legacy unlock all operation > - the > outcome will be the same. It will either keep being locked or all will > be > unlocked. In case WP# is asserted, we'll catch this via the dev_dbg message in spi_nor_write_sr_and_check() when trying to clear the SRWD bit. We will have an idea of what's going on, instead of a silent fail to unlock. > > That being said, I can also change it to the same as the > global_unprotect(). > I don't have any option on that other than this is simpler. > > -michael
diff --git a/drivers/mtd/spi-nor/atmel.c b/drivers/mtd/spi-nor/atmel.c index 49d392c6c8bc..fe6a4653823d 100644 --- a/drivers/mtd/spi-nor/atmel.c +++ b/drivers/mtd/spi-nor/atmel.c @@ -8,10 +8,59 @@ #include "core.h" +/* + * The Atmel AT25FS010/AT25FS040 parts have some weird configuration for the + * block protection bits. We don't support them. But legacy behaviour in linux + * is to unlock the whole flash array on startup. Therefore, we have to support + * exactly this operation. + */ +static int atmel_at25fs_lock(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + return -EOPNOTSUPP; +} + +static int atmel_at25fs_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + /* We only support unlocking the whole flash array */ + if (ofs || len != nor->params->size) + return -EINVAL; + + /* + * Write 0x00 to the status register to try to disable the write + * protection. This will fail if SRWD (the datasheet calls it WPEN) is + * set. But there is nothing we can do. + */ + nor->bouncebuf[0] = 0; + + return spi_nor_write_sr(nor, nor->bouncebuf, 1); +} + +static int atmel_at25fs_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len) +{ + return -EOPNOTSUPP; +} + +static const struct spi_nor_locking_ops atmel_at25fs_locking_ops = { + .lock = atmel_at25fs_lock, + .unlock = atmel_at25fs_unlock, + .is_locked = atmel_at25fs_is_locked, +}; + +static void atmel_at25fs_default_init(struct spi_nor *nor) +{ + nor->params->locking_ops = &atmel_at25fs_locking_ops; +} + +static const struct spi_nor_fixups atmel_at25fs_fixups = { + .default_init = atmel_at25fs_default_init, +}; + static const struct flash_info atmel_parts[] = { /* Atmel -- some are (confusingly) marketed as "DataFlash" */ - { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K | SPI_NOR_HAS_LOCK) }, - { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) }, + { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K | SPI_NOR_HAS_LOCK) + .fixups = &atmel_at25fs_fixups }, + { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) + .fixups = &atmel_at25fs_fixups }, { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K | SPI_NOR_HAS_LOCK) }, { "at25df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) }, diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 5bee7c8da4dc..8c06a28a90de 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -861,7 +861,7 @@ int spi_nor_wait_till_ready(struct spi_nor *nor) * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) +int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) { int ret; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 0a775a7b5606..16b350e1d865 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -430,6 +430,7 @@ void spi_nor_unlock_and_unprep(struct spi_nor *nor); int spi_nor_sr1_bit6_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit1_quad_enable(struct spi_nor *nor); int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor); +int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len); int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr); ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len,
These flashes have some weird BP bits mapping which aren't supported in the current locking code. Just add a simple unlock op to unprotect the entire flash array which is needed for legacy behavior. Signed-off-by: Michael Walle <michael@walle.cc> --- changes since v5 - new patch drivers/mtd/spi-nor/atmel.c | 53 +++++++++++++++++++++++++++++++++++-- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 1 + 3 files changed, 53 insertions(+), 3 deletions(-)