| Message ID | 20200930185732.6201-9-p.yadav@ti.com |
|---|---|
| State | Superseded |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | mtd: spi-nor: add xSPI Octal DTR support | expand |
On 9/30/20 9:57 PM, Pratyush Yadav wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Allow flashes to specify a hook to enable octal DTR mode. Use this hook > whenever possible to get optimal transfer speeds. > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > --- > drivers/mtd/spi-nor/core.c | 35 +++++++++++++++++++++++++++++++++++ > drivers/mtd/spi-nor/core.h | 2 ++ > 2 files changed, 37 insertions(+) > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > index 73a26e7e32c2..6b54a923002a 100644 > --- a/drivers/mtd/spi-nor/core.c > +++ b/drivers/mtd/spi-nor/core.c > @@ -3068,6 +3068,35 @@ static int spi_nor_init_params(struct spi_nor *nor) > return 0; > } > > +/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed > + * @nor: pointer to a 'struct spi_nor' > + * @enable: whether to enable or disable Octal DTR > + * > + * Return: 0 on success, -errno otherwise. > + */ > +static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) > +{ > + int ret; > + > + if (!nor->params->octal_dtr_enable) > + return 0; > + > + if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && > + nor->write_proto == SNOR_PROTO_8_8_8_DTR)) > + return 0; > + > + ret = nor->params->octal_dtr_enable(nor, enable); Ideally patch 9/15 and 10/15 should have been before 8/15. We should deny the access to octal dtr enable for NV flashes since moment 0. > + if (ret) > + return ret; > + > + if (enable) > + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; > + else > + nor->reg_proto = SNOR_PROTO_1_1_1; > + > + return 0; > +} > + > /** > * spi_nor_quad_enable() - enable Quad I/O if needed. > * @nor: pointer to a 'struct spi_nor' > @@ -3107,6 +3136,12 @@ static int spi_nor_init(struct spi_nor *nor) > { > int err; > > + err = spi_nor_octal_dtr_enable(nor, true); > + if (err) { > + dev_dbg(nor->dev, "octal mode not supported\n"); > + return err; > + } > + > err = spi_nor_quad_enable(nor); > if (err) { > dev_dbg(nor->dev, "quad mode not supported\n"); > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > index 9a33c8d07335..5cfe2db9ee13 100644 > --- a/drivers/mtd/spi-nor/core.h > +++ b/drivers/mtd/spi-nor/core.h > @@ -203,6 +203,7 @@ struct spi_nor_locking_ops { > * higher index in the array, the higher priority. > * @erase_map: the erase map parsed from the SFDP Sector Map Parameter > * Table. > + * @octal_dtr_enable: enables SPI NOR octal DTR mode. > * @quad_enable: enables SPI NOR quad mode. > * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. > * @convert_addr: converts an absolute address into something the flash > @@ -226,6 +227,7 @@ struct spi_nor_flash_parameter { > > struct spi_nor_erase_map erase_map; > > + int (*octal_dtr_enable)(struct spi_nor *nor, bool enable); > int (*quad_enable)(struct spi_nor *nor); > int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); > u32 (*convert_addr)(struct spi_nor *nor, u32 addr); > -- > 2.28.0 >
On 01/10/20 08:09AM, Tudor.Ambarus@microchip.com wrote: > On 9/30/20 9:57 PM, Pratyush Yadav wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Allow flashes to specify a hook to enable octal DTR mode. Use this hook > > whenever possible to get optimal transfer speeds. > > > > Signed-off-by: Pratyush Yadav <p.yadav@ti.com> > > --- > > drivers/mtd/spi-nor/core.c | 35 +++++++++++++++++++++++++++++++++++ > > drivers/mtd/spi-nor/core.h | 2 ++ > > 2 files changed, 37 insertions(+) > > > > diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c > > index 73a26e7e32c2..6b54a923002a 100644 > > --- a/drivers/mtd/spi-nor/core.c > > +++ b/drivers/mtd/spi-nor/core.c > > @@ -3068,6 +3068,35 @@ static int spi_nor_init_params(struct spi_nor *nor) > > return 0; > > } > > > > +/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed > > + * @nor: pointer to a 'struct spi_nor' > > + * @enable: whether to enable or disable Octal DTR > > + * > > + * Return: 0 on success, -errno otherwise. > > + */ > > +static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) > > +{ > > + int ret; > > + > > + if (!nor->params->octal_dtr_enable) > > + return 0; > > + > > + if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && > > + nor->write_proto == SNOR_PROTO_8_8_8_DTR)) > > + return 0; > > + > > + ret = nor->params->octal_dtr_enable(nor, enable); > > Ideally patch 9/15 and 10/15 should have been before 8/15. We should deny > the access to octal dtr enable for NV flashes since moment 0. Ok. I'll re-order them. > > + if (ret) > > + return ret; > > + > > + if (enable) > > + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; > > + else > > + nor->reg_proto = SNOR_PROTO_1_1_1; > > + > > + return 0; > > +} > > + > > /** > > * spi_nor_quad_enable() - enable Quad I/O if needed. > > * @nor: pointer to a 'struct spi_nor' > > @@ -3107,6 +3136,12 @@ static int spi_nor_init(struct spi_nor *nor) > > { > > int err; > > > > + err = spi_nor_octal_dtr_enable(nor, true); > > + if (err) { > > + dev_dbg(nor->dev, "octal mode not supported\n"); > > + return err; > > + } > > + > > err = spi_nor_quad_enable(nor); > > if (err) { > > dev_dbg(nor->dev, "quad mode not supported\n"); > > diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h > > index 9a33c8d07335..5cfe2db9ee13 100644 > > --- a/drivers/mtd/spi-nor/core.h > > +++ b/drivers/mtd/spi-nor/core.h > > @@ -203,6 +203,7 @@ struct spi_nor_locking_ops { > > * higher index in the array, the higher priority. > > * @erase_map: the erase map parsed from the SFDP Sector Map Parameter > > * Table. > > + * @octal_dtr_enable: enables SPI NOR octal DTR mode. > > * @quad_enable: enables SPI NOR quad mode. > > * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. > > * @convert_addr: converts an absolute address into something the flash > > @@ -226,6 +227,7 @@ struct spi_nor_flash_parameter { > > > > struct spi_nor_erase_map erase_map; > > > > + int (*octal_dtr_enable)(struct spi_nor *nor, bool enable); > > int (*quad_enable)(struct spi_nor *nor); > > int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); > > u32 (*convert_addr)(struct spi_nor *nor, u32 addr); > > -- > > 2.28.0 > > >
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 73a26e7e32c2..6b54a923002a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3068,6 +3068,35 @@ static int spi_nor_init_params(struct spi_nor *nor) return 0; } +/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed + * @nor: pointer to a 'struct spi_nor' + * @enable: whether to enable or disable Octal DTR + * + * Return: 0 on success, -errno otherwise. + */ +static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable) +{ + int ret; + + if (!nor->params->octal_dtr_enable) + return 0; + + if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR && + nor->write_proto == SNOR_PROTO_8_8_8_DTR)) + return 0; + + ret = nor->params->octal_dtr_enable(nor, enable); + if (ret) + return ret; + + if (enable) + nor->reg_proto = SNOR_PROTO_8_8_8_DTR; + else + nor->reg_proto = SNOR_PROTO_1_1_1; + + return 0; +} + /** * spi_nor_quad_enable() - enable Quad I/O if needed. * @nor: pointer to a 'struct spi_nor' @@ -3107,6 +3136,12 @@ static int spi_nor_init(struct spi_nor *nor) { int err; + err = spi_nor_octal_dtr_enable(nor, true); + if (err) { + dev_dbg(nor->dev, "octal mode not supported\n"); + return err; + } + err = spi_nor_quad_enable(nor); if (err) { dev_dbg(nor->dev, "quad mode not supported\n"); diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 9a33c8d07335..5cfe2db9ee13 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -203,6 +203,7 @@ struct spi_nor_locking_ops { * higher index in the array, the higher priority. * @erase_map: the erase map parsed from the SFDP Sector Map Parameter * Table. + * @octal_dtr_enable: enables SPI NOR octal DTR mode. * @quad_enable: enables SPI NOR quad mode. * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. * @convert_addr: converts an absolute address into something the flash @@ -226,6 +227,7 @@ struct spi_nor_flash_parameter { struct spi_nor_erase_map erase_map; + int (*octal_dtr_enable)(struct spi_nor *nor, bool enable); int (*quad_enable)(struct spi_nor *nor); int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable); u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
Allow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> --- drivers/mtd/spi-nor/core.c | 35 +++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 2 ++ 2 files changed, 37 insertions(+)