| Message ID | 20200528231612.8958-17-miquel.raynal@bootlin.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Miquel Raynal |
| Headers | show |
| Series | Allow vendor drivers to propose their own timings | expand |
On Fri, 29 May 2020 01:15:58 +0200 Miquel Raynal <miquel.raynal@bootlin.com> wrote: > The ONFI parameter page of a chip might define more fine grained > tPROG_max and tBERS_max. When we do not have this information, we > default to the highest possible values (they are maxima anyway). > > There is no point setting these fields at runtime, so explicitly move > these defaults to the main ONFI SDR timings structure. And most importantly you want to do that to return a pointer to mode 0 directly :P. > > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> > --- > drivers/mtd/nand/raw/nand_timings.c | 31 ++++++++++++++++++----------- > 1 file changed, 19 insertions(+), 12 deletions(-) > > diff --git a/drivers/mtd/nand/raw/nand_timings.c b/drivers/mtd/nand/raw/nand_timings.c > index 728a2dee1eed..9ff4b121ab1e 100644 > --- a/drivers/mtd/nand/raw/nand_timings.c > +++ b/drivers/mtd/nand/raw/nand_timings.c > @@ -12,6 +12,13 @@ > > #define ONFI_DYN_TIMING_MAX U16_MAX > > +/* > + * For non-ONFI chips we use the highest possible value for tPROG and tBERS. > + * tR and tCCS will take the default values precised in the ONFI specification > + * for timing mode 0, respectively 200us and 500ns. > + * > + * These four values are tweaked to be more accurate in the case of ONFI chips. > + */ > static const struct nand_data_interface onfi_sdr_timings[] = { > /* Mode 0 */ > { > @@ -20,6 +27,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { > .timings.sdr = { > .tCCS_min = 500000, > .tR_max = 200000000, > + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > .tADL_min = 400000, > .tALH_min = 20000, > .tALS_min = 50000, > @@ -63,6 +72,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { > .timings.sdr = { > .tCCS_min = 500000, > .tR_max = 200000000, > + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > .tADL_min = 400000, > .tALH_min = 10000, > .tALS_min = 25000, > @@ -106,6 +117,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { > .timings.sdr = { > .tCCS_min = 500000, > .tR_max = 200000000, > + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > .tADL_min = 400000, > .tALH_min = 10000, > .tALS_min = 15000, > @@ -149,6 +162,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { > .timings.sdr = { > .tCCS_min = 500000, > .tR_max = 200000000, > + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > .tADL_min = 400000, > .tALH_min = 5000, > .tALS_min = 10000, > @@ -192,6 +207,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { > .timings.sdr = { > .tCCS_min = 500000, > .tR_max = 200000000, > + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > .tADL_min = 400000, > .tALH_min = 5000, > .tALS_min = 10000, > @@ -235,6 +252,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { > .timings.sdr = { > .tCCS_min = 500000, > .tR_max = 200000000, > + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, > .tADL_min = 400000, > .tALH_min = 5000, > .tALS_min = 10000, > @@ -357,18 +376,6 @@ int onfi_fill_data_interface(struct nand_chip *chip, > > /* nanoseconds -> picoseconds */ > timings->tCCS_min = 1000UL * onfi->tCCS; > - } else { > - struct nand_sdr_timings *timings = &iface->timings.sdr; > - /* > - * For non-ONFI chips we use the highest possible value for > - * tPROG and tBERS. tR and tCCS will take the default values > - * precised in the ONFI specification for timing mode 0, > - * respectively 200us and 500ns. > - */ > - > - /* microseconds -> picoseconds */ > - timings->tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX; > - timings->tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX; > } > > return 0;
diff --git a/drivers/mtd/nand/raw/nand_timings.c b/drivers/mtd/nand/raw/nand_timings.c index 728a2dee1eed..9ff4b121ab1e 100644 --- a/drivers/mtd/nand/raw/nand_timings.c +++ b/drivers/mtd/nand/raw/nand_timings.c @@ -12,6 +12,13 @@ #define ONFI_DYN_TIMING_MAX U16_MAX +/* + * For non-ONFI chips we use the highest possible value for tPROG and tBERS. + * tR and tCCS will take the default values precised in the ONFI specification + * for timing mode 0, respectively 200us and 500ns. + * + * These four values are tweaked to be more accurate in the case of ONFI chips. + */ static const struct nand_data_interface onfi_sdr_timings[] = { /* Mode 0 */ { @@ -20,6 +27,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { .timings.sdr = { .tCCS_min = 500000, .tR_max = 200000000, + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, .tADL_min = 400000, .tALH_min = 20000, .tALS_min = 50000, @@ -63,6 +72,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { .timings.sdr = { .tCCS_min = 500000, .tR_max = 200000000, + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, .tADL_min = 400000, .tALH_min = 10000, .tALS_min = 25000, @@ -106,6 +117,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { .timings.sdr = { .tCCS_min = 500000, .tR_max = 200000000, + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, .tADL_min = 400000, .tALH_min = 10000, .tALS_min = 15000, @@ -149,6 +162,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { .timings.sdr = { .tCCS_min = 500000, .tR_max = 200000000, + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, .tADL_min = 400000, .tALH_min = 5000, .tALS_min = 10000, @@ -192,6 +207,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { .timings.sdr = { .tCCS_min = 500000, .tR_max = 200000000, + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, .tADL_min = 400000, .tALH_min = 5000, .tALS_min = 10000, @@ -235,6 +252,8 @@ static const struct nand_data_interface onfi_sdr_timings[] = { .timings.sdr = { .tCCS_min = 500000, .tR_max = 200000000, + .tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX, + .tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX, .tADL_min = 400000, .tALH_min = 5000, .tALS_min = 10000, @@ -357,18 +376,6 @@ int onfi_fill_data_interface(struct nand_chip *chip, /* nanoseconds -> picoseconds */ timings->tCCS_min = 1000UL * onfi->tCCS; - } else { - struct nand_sdr_timings *timings = &iface->timings.sdr; - /* - * For non-ONFI chips we use the highest possible value for - * tPROG and tBERS. tR and tCCS will take the default values - * precised in the ONFI specification for timing mode 0, - * respectively 200us and 500ns. - */ - - /* microseconds -> picoseconds */ - timings->tPROG_max = 1000000ULL * ONFI_DYN_TIMING_MAX; - timings->tBERS_max = 1000000ULL * ONFI_DYN_TIMING_MAX; } return 0;
The ONFI parameter page of a chip might define more fine grained tPROG_max and tBERS_max. When we do not have this information, we default to the highest possible values (they are maxima anyway). There is no point setting these fields at runtime, so explicitly move these defaults to the main ONFI SDR timings structure. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/mtd/nand/raw/nand_timings.c | 31 ++++++++++++++++++----------- 1 file changed, 19 insertions(+), 12 deletions(-)