| Message ID | 20200525174239.11349-20-miquel.raynal@bootlin.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Miquel Raynal |
| Headers | show |
| Series | Allow vendor drivers to propose their own timings | expand |
On Mon, 25 May 2020 19:42:39 +0200 Miquel Raynal <miquel.raynal@bootlin.com> wrote: > From: Rickard x Andersson <rickaran@axis.com> > > The Kioxia/Toshiba TH58NVG2S3HBAI4 NAND memory is not ONFI compliant. > The timings of the NAND chip memory are quite close to ONFI mode 4 but > is breaking that spec. > > By providing our own set of timings, erase block read speed is increased > from 6910 kiB/s to 13490 kiB/s and erase block write speed is increased > from 3350 kiB/s to 4410 kiB/s. > > Tested on IMX6SX which has a NAND controller supporting EDO mode. > > Signed-off-by: Rickard x Andersson <rickaran@axis.com> > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> > --- > drivers/mtd/nand/raw/nand_ids.c | 3 +++ > drivers/mtd/nand/raw/nand_toshiba.c | 38 +++++++++++++++++++++++++++++ > 2 files changed, 41 insertions(+) > > diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c > index e0dbc2e316c7..8b676e8b481b 100644 > --- a/drivers/mtd/nand/raw/nand_ids.c > +++ b/drivers/mtd/nand/raw/nand_ids.c > @@ -52,6 +52,9 @@ struct nand_flash_dev nand_flash_ids[] = { > { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, > SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, > NAND_ECC_INFO(40, SZ_1K), 4 }, > + {"TH58NVG2S3HBAI4 4G 3.3V 8-bit", > + { .id = {0x98, 0xdc, 0x91, 0x15, 0x76} }, > + SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) }, > > LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), > LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), > diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c > index b6efaf5195bb..6c79464fdf34 100644 > --- a/drivers/mtd/nand/raw/nand_toshiba.c > +++ b/drivers/mtd/nand/raw/nand_toshiba.c > @@ -205,6 +205,42 @@ static int tc58teg5dclta00_init(struct nand_chip *chip) > return 0; > } > > +static int th58nvg2s3hbai4_choose_data_interface(struct nand_chip *chip) > +{ > + struct nand_data_interface iface; > + struct nand_sdr_timings *sdr = &iface.timings.sdr; > + int ret; > + > + /* Start with timings from the closest timing mode, mode 4. */ > + ret = onfi_fill_data_interface(chip, &iface, NAND_SDR_IFACE, 4); > + if (ret) > + return ret; > + > + /* Patch timings that differ from mode 4. */ > + sdr->tALS_min = 12000; > + sdr->tCHZ_max = 20000; > + sdr->tCLS_min = 12000; > + sdr->tCOH_min = 0; > + sdr->tDS_min = 12000; > + sdr->tRHOH_min = 25000; > + sdr->tRHW_min = 30000; > + sdr->tRHZ_max = 60000; > + sdr->tWHR_min = 60000; > + > + /* Patch timings not part of onfi timing mode. */ > + sdr->tPROG_max = 700000000; > + sdr->tBERS_max = 5000000000; Yay! That's much better than redefining all timings. > + > + return nand_choose_best_vendor_sdr_iface(chip, &iface); > +} > + > +static int th58nvg2s3hbai4_init(struct nand_chip *chip) > +{ > + chip->ops.choose_data_interface = th58nvg2s3hbai4_choose_data_interface; > + > + return 0; > +} > + > static int toshiba_nand_init(struct nand_chip *chip) > { > if (nand_is_slc(chip)) > @@ -217,6 +253,8 @@ static int toshiba_nand_init(struct nand_chip *chip) > > if (!strcmp("TC58TEG5DCLTA00", chip->parameters.model)) > tc58teg5dclta00_init(chip); As said previously, I'd prefer to have a patch using the same approach for TC58TEG5DCLTA00. > + if (!strncmp("TH58NVG2S3HBAI4", chip->parameters.model, 15)) > + th58nvg2s3hbai4_init(chip); > > return 0; > }
diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index e0dbc2e316c7..8b676e8b481b 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -52,6 +52,9 @@ struct nand_flash_dev nand_flash_ids[] = { { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, NAND_ECC_INFO(40, SZ_1K), 4 }, + {"TH58NVG2S3HBAI4 4G 3.3V 8-bit", + { .id = {0x98, 0xdc, 0x91, 0x15, 0x76} }, + SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) }, LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), diff --git a/drivers/mtd/nand/raw/nand_toshiba.c b/drivers/mtd/nand/raw/nand_toshiba.c index b6efaf5195bb..6c79464fdf34 100644 --- a/drivers/mtd/nand/raw/nand_toshiba.c +++ b/drivers/mtd/nand/raw/nand_toshiba.c @@ -205,6 +205,42 @@ static int tc58teg5dclta00_init(struct nand_chip *chip) return 0; } +static int th58nvg2s3hbai4_choose_data_interface(struct nand_chip *chip) +{ + struct nand_data_interface iface; + struct nand_sdr_timings *sdr = &iface.timings.sdr; + int ret; + + /* Start with timings from the closest timing mode, mode 4. */ + ret = onfi_fill_data_interface(chip, &iface, NAND_SDR_IFACE, 4); + if (ret) + return ret; + + /* Patch timings that differ from mode 4. */ + sdr->tALS_min = 12000; + sdr->tCHZ_max = 20000; + sdr->tCLS_min = 12000; + sdr->tCOH_min = 0; + sdr->tDS_min = 12000; + sdr->tRHOH_min = 25000; + sdr->tRHW_min = 30000; + sdr->tRHZ_max = 60000; + sdr->tWHR_min = 60000; + + /* Patch timings not part of onfi timing mode. */ + sdr->tPROG_max = 700000000; + sdr->tBERS_max = 5000000000; + + return nand_choose_best_vendor_sdr_iface(chip, &iface); +} + +static int th58nvg2s3hbai4_init(struct nand_chip *chip) +{ + chip->ops.choose_data_interface = th58nvg2s3hbai4_choose_data_interface; + + return 0; +} + static int toshiba_nand_init(struct nand_chip *chip) { if (nand_is_slc(chip)) @@ -217,6 +253,8 @@ static int toshiba_nand_init(struct nand_chip *chip) if (!strcmp("TC58TEG5DCLTA00", chip->parameters.model)) tc58teg5dclta00_init(chip); + if (!strncmp("TH58NVG2S3HBAI4", chip->parameters.model, 15)) + th58nvg2s3hbai4_init(chip); return 0; }