Message ID | 20190827035827.21024-2-vadivel.muruganx.ramuthevar@linux.intel.com |
---|---|
State | Accepted |
Headers | show |
Series | dt-bindings: mtd: cadence-qspi:add support for Intel lgm-qspi | expand |
On Tue, 27 Aug 2019 11:58:25 +0800, "Ramuthevar,Vadivel MuruganX" wrote: > From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > > Add new vendor specific compatible string to check Intel's Lightning > Mountain(LGM) QSPI features enablement in cadence-quadspi driver. > > Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> > --- > Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
Hi Rob, Thank you for the review and Acked-by. On 2/9/2019 9:39 PM, Rob Herring wrote: > On Tue, 27 Aug 2019 11:58:25 +0800, "Ramuthevar,Vadivel MuruganX" wrote: >> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> >> Add new vendor specific compatible string to check Intel's Lightning >> Mountain(LGM) QSPI features enablement in cadence-quadspi driver. >> >> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> >> --- >> Documentation/devicetree/bindings/mtd/cadence-quadspi.txt | 1 + >> 1 file changed, 1 insertion(+) >> > Acked-by: Rob Herring <robh@kernel.org> Acked-by tag will be updated in next patch-set. Best Regards Vadivel
diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt index 945be7d5b236..8ace832a2d80 100644 --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt +++ b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt @@ -5,6 +5,7 @@ Required properties: Generic default - "cdns,qspi-nor". For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor". + For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor". - reg : Contains two entries, each of which is a tuple consisting of a physical address and length. The first entry is the address and length of the controller register set. The second entry is the