| Message ID | 20190613113138.8280-2-dinguyen@kernel.org |
|---|---|
| State | Accepted |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | [PATCHv6,1/2] dt-bindings: cadence-quadspi: add options reset property | expand |
Hi, Dinh, On 06/13/2019 02:31 PM, Dinh Nguyen wrote: > + struct reset_control *rstc; > + struct reset_control *rstc_ocp; I'll add these on a single line when applying. The patch is good, I'm waiting for Rob to review the bindings. Thanks, ta
Hi Tudor, On 6/22/19 5:21 AM, Tudor.Ambarus@microchip.com wrote: > Hi, Dinh, > > On 06/13/2019 02:31 PM, Dinh Nguyen wrote: >> + struct reset_control *rstc; >> + struct reset_control *rstc_ocp; > > I'll add these on a single line when applying. The patch is good, I'm waiting > for Rob to review the bindings. > Thanks! Dinh
On 13/06/19 5:01 PM, Dinh Nguyen wrote: > Get the reset control properties for the QSPI controller and bring them > out of reset. Most will have just one reset bit, but there is an additional > OCP reset bit that is used ECC. The OCP reset bit will also need to get > de-asserted as well. [1] > > The reason this patch is needed is in the case where a bootloader leaves > the QSPI controller in a reset state, or a state where init cannot occur > successfully, the patch will put the QSPI controller into a clean state. > > [1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html > > Suggested-by: Tien-Fong Chee <tien.fong.chee@intel.com> > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Regards Vignesh > v6: no need to check for reset pointer in assert/deassert as the call to > assert/deassert is already doing the checking > v5: remove udelay(not needed) on tested hardware > group reset assert/deassert together > update commit message with reasoning for patch > v4: fix compile error > v3: return full error by using PTR_ERR(rtsc) > move reset control calls until after the clock enables > use udelay(2) to be safe > Add optional OCP(Open Core Protocol) reset signal > v2: use devm_reset_control_get_optional_exclusive > print an error message > return -EPROBE_DEFER > --- > drivers/mtd/spi-nor/cadence-quadspi.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c > index 792628750eec..732323c2adb1 100644 > --- a/drivers/mtd/spi-nor/cadence-quadspi.c > +++ b/drivers/mtd/spi-nor/cadence-quadspi.c > @@ -34,6 +34,7 @@ > #include <linux/of.h> > #include <linux/platform_device.h> > #include <linux/pm_runtime.h> > +#include <linux/reset.h> > #include <linux/sched.h> > #include <linux/spi/spi.h> > #include <linux/timer.h> > @@ -1336,6 +1337,8 @@ static int cqspi_probe(struct platform_device *pdev) > struct cqspi_st *cqspi; > struct resource *res; > struct resource *res_ahb; > + struct reset_control *rstc; > + struct reset_control *rstc_ocp; > const struct cqspi_driver_platdata *ddata; > int ret; > int irq; > @@ -1402,6 +1405,25 @@ static int cqspi_probe(struct platform_device *pdev) > goto probe_clk_failed; > } > > + /* Obtain QSPI reset control */ > + rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); > + if (IS_ERR(rstc)) { > + dev_err(dev, "Cannot get QSPI reset.\n"); > + return PTR_ERR(rstc); > + } > + > + rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); > + if (IS_ERR(rstc_ocp)) { > + dev_err(dev, "Cannot get QSPI OCP reset.\n"); > + return PTR_ERR(rstc_ocp); > + } > + > + reset_control_assert(rstc); > + reset_control_deassert(rstc); > + > + reset_control_assert(rstc_ocp); > + reset_control_deassert(rstc_ocp); > + > cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); > ddata = of_device_get_match_data(dev); > if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) >
On 06/13/2019 02:31 PM, Dinh Nguyen wrote: > External E-Mail > > > Get the reset control properties for the QSPI controller and bring them > out of reset. Most will have just one reset bit, but there is an additional > OCP reset bit that is used ECC. The OCP reset bit will also need to get > de-asserted as well. [1] > > The reason this patch is needed is in the case where a bootloader leaves > the QSPI controller in a reset state, or a state where init cannot occur > successfully, the patch will put the QSPI controller into a clean state. > > [1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html > > Suggested-by: Tien-Fong Chee <tien.fong.chee@intel.com> > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > v6: no need to check for reset pointer in assert/deassert as the call to > assert/deassert is already doing the checking > v5: remove udelay(not needed) on tested hardware > group reset assert/deassert together > update commit message with reasoning for patch > v4: fix compile error > v3: return full error by using PTR_ERR(rtsc) > move reset control calls until after the clock enables > use udelay(2) to be safe > Add optional OCP(Open Core Protocol) reset signal > v2: use devm_reset_control_get_optional_exclusive > print an error message > return -EPROBE_DEFER > --- > drivers/mtd/spi-nor/cadence-quadspi.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c > index 792628750eec..732323c2adb1 100644 > --- a/drivers/mtd/spi-nor/cadence-quadspi.c > +++ b/drivers/mtd/spi-nor/cadence-quadspi.c > @@ -34,6 +34,7 @@ > #include <linux/of.h> > #include <linux/platform_device.h> > #include <linux/pm_runtime.h> > +#include <linux/reset.h> > #include <linux/sched.h> > #include <linux/spi/spi.h> > #include <linux/timer.h> > @@ -1336,6 +1337,8 @@ static int cqspi_probe(struct platform_device *pdev) > struct cqspi_st *cqspi; > struct resource *res; > struct resource *res_ahb; > + struct reset_control *rstc; > + struct reset_control *rstc_ocp; declare rstc and rstc_ocp on the same line and Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git, spi-nor/next branch. Thanks, ta > const struct cqspi_driver_platdata *ddata; > int ret; > int irq; > @@ -1402,6 +1405,25 @@ static int cqspi_probe(struct platform_device *pdev) > goto probe_clk_failed; > } > > + /* Obtain QSPI reset control */ > + rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); > + if (IS_ERR(rstc)) { > + dev_err(dev, "Cannot get QSPI reset.\n"); > + return PTR_ERR(rstc); > + } > + > + rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); > + if (IS_ERR(rstc_ocp)) { > + dev_err(dev, "Cannot get QSPI OCP reset.\n"); > + return PTR_ERR(rstc_ocp); > + } > + > + reset_control_assert(rstc); > + reset_control_deassert(rstc); > + > + reset_control_assert(rstc_ocp); > + reset_control_deassert(rstc_ocp); > + > cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); > ddata = of_device_get_match_data(dev); > if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY)) >
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 792628750eec..732323c2adb1 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -34,6 +34,7 @@ #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> +#include <linux/reset.h> #include <linux/sched.h> #include <linux/spi/spi.h> #include <linux/timer.h> @@ -1336,6 +1337,8 @@ static int cqspi_probe(struct platform_device *pdev) struct cqspi_st *cqspi; struct resource *res; struct resource *res_ahb; + struct reset_control *rstc; + struct reset_control *rstc_ocp; const struct cqspi_driver_platdata *ddata; int ret; int irq; @@ -1402,6 +1405,25 @@ static int cqspi_probe(struct platform_device *pdev) goto probe_clk_failed; } + /* Obtain QSPI reset control */ + rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); + if (IS_ERR(rstc)) { + dev_err(dev, "Cannot get QSPI reset.\n"); + return PTR_ERR(rstc); + } + + rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); + if (IS_ERR(rstc_ocp)) { + dev_err(dev, "Cannot get QSPI OCP reset.\n"); + return PTR_ERR(rstc_ocp); + } + + reset_control_assert(rstc); + reset_control_deassert(rstc); + + reset_control_assert(rstc_ocp); + reset_control_deassert(rstc_ocp); + cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); ddata = of_device_get_match_data(dev); if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
Get the reset control properties for the QSPI controller and bring them out of reset. Most will have just one reset bit, but there is an additional OCP reset bit that is used ECC. The OCP reset bit will also need to get de-asserted as well. [1] The reason this patch is needed is in the case where a bootloader leaves the QSPI controller in a reset state, or a state where init cannot occur successfully, the patch will put the QSPI controller into a clean state. [1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html Suggested-by: Tien-Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- v6: no need to check for reset pointer in assert/deassert as the call to assert/deassert is already doing the checking v5: remove udelay(not needed) on tested hardware group reset assert/deassert together update commit message with reasoning for patch v4: fix compile error v3: return full error by using PTR_ERR(rtsc) move reset control calls until after the clock enables use udelay(2) to be safe Add optional OCP(Open Core Protocol) reset signal v2: use devm_reset_control_get_optional_exclusive print an error message return -EPROBE_DEFER --- drivers/mtd/spi-nor/cadence-quadspi.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)