From patchwork Wed May 8 13:43:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 1097041 X-Patchwork-Delegate: tudor.ambarus@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uf471XSm"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="CdP1f7IL"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 44zd456cJVz9sDn for ; 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Wed, 08 May 2019 13:44:01 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hOMrR-0005Lf-9c for linux-mtd@lists.infradead.org; Wed, 08 May 2019 13:43:54 +0000 Received: from localhost.localdomain (cpe-70-114-128-244.austin.res.rr.com [70.114.128.244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 2B762216B7; Wed, 8 May 2019 13:43:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1557323033; bh=OJmgP1E+mmtjTsf1WtejtNwHG6Y398f4yIiaqFrrEiI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CdP1f7ILZqBPw2BMpB4qJDVKL+7JgHgaXfvD05pl9bLGdggralLbG1nqusElIuLzk +V4NFW49BWaHn0+jNsT3dT7A6EcCbx1yJHNdEHM1DR9ZK5EZO2KMnyVP2rZ9dIz0Zn GSMp1fayn7tbMI5icg6rWM+bxbIsWbmdYPpmY70U= From: Dinh Nguyen To: linux-mtd@lists.infradead.org Subject: [PATCHv4 2/2] mtd: spi-nor: cadence-quadspi: add reset control Date: Wed, 8 May 2019 08:43:38 -0500 Message-Id: <20190508134338.20565-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.20.0 In-Reply-To: <20190508134338.20565-1-dinguyen@kernel.org> References: <20190508134338.20565-1-dinguyen@kernel.org> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190508_064353_349462_D100E5E3 X-CRM114-Status: GOOD ( 11.26 ) X-Spam-Score: -5.2 (-----) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-5.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 T_DKIMWL_WL_HIGH DKIMwl.org - Whitelisted High sender X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, devicetree@vger.kernel.org, Tien-Fong Chee , bbrezillon@kernel.org, tudor.ambarus@microchip.com, linux-kernel@vger.kernel.org, dinguyen@kernel.org, computersforpeace@gmail.com, dwmw2@infradead.org Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Get the reset control properties for the QSPI controller and bring them out of reset. Most will have just one reset bit, but there is an additional OCP reset bit that is used ECC. The OCP reset bit will also need to get de-asserted as well. [1] [1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html Suggested-by: Tien-Fong Chee Signed-off-by: Dinh Nguyen --- v4: fix compile error v3: return full error by using PTR_ERR(rtsc) move reset control calls until after the clock enables use udelay(2) to be safe Add optional OCP(Open Core Protocol) reset signal v2: use devm_reset_control_get_optional_exclusive print an error message return -EPROBE_DEFER --- drivers/mtd/spi-nor/cadence-quadspi.c | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 792628750eec..d3906e5a1d44 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -1336,6 +1337,8 @@ static int cqspi_probe(struct platform_device *pdev) struct cqspi_st *cqspi; struct resource *res; struct resource *res_ahb; + struct reset_control *rstc; + struct reset_control *rstc_ocp; const struct cqspi_driver_platdata *ddata; int ret; int irq; @@ -1402,6 +1405,33 @@ static int cqspi_probe(struct platform_device *pdev) goto probe_clk_failed; } + /* Obtain QSPI reset control */ + rstc = devm_reset_control_get_optional_exclusive(dev, "qspi"); + if (IS_ERR(rstc)) { + dev_err(dev, "Cannot get QSPI reset.\n"); + if (PTR_ERR(rstc) == -EPROBE_DEFER) + return PTR_ERR(rstc); + } + + rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); + if (IS_ERR(rstc_ocp)) { + dev_err(dev, "Cannot get QSPI OCP reset.\n"); + if (PTR_ERR(rstc_ocp) == -EPROBE_DEFER) + return PTR_ERR(rstc_ocp); + } + + if (rstc) { + reset_control_assert(rstc); + udelay(2); + reset_control_deassert(rstc); + } + + if (rstc_ocp) { + reset_control_assert(rstc_ocp); + udelay(2); + reset_control_deassert(rstc_ocp); + } + cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); ddata = of_device_get_match_data(dev); if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))