@@ -800,6 +800,12 @@ static int mtdchar_ioctl(struct file *file, u_int cmd, u_long arg)
break;
}
+ case MEMSETPOWERUPLOCK:
+ {
+ ret = mtd_set_powerup_lock(mtd);
+ break;
+ }
+
case MEMLOCK:
{
struct erase_info_user einfo;
@@ -1681,6 +1681,14 @@ int mtd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from, size_t len)
}
EXPORT_SYMBOL_GPL(mtd_lock_user_prot_reg);
+int mtd_set_powerup_lock(struct mtd_info *mtd)
+{
+ if (!mtd->_set_powerup_lock)
+ return -EOPNOTSUPP;
+ return mtd->_set_powerup_lock(mtd);
+}
+EXPORT_SYMBOL_GPL(mtd_set_powerup_lock);
+
/* Chip-supported device locking */
int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
@@ -250,7 +250,7 @@ struct flash_info {
u16 page_size;
u16 addr_width;
- u16 flags;
+ u32 flags;
#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
#define SST_WRITE BIT(2) /* use SST byte programming */
@@ -279,6 +279,11 @@ struct flash_info {
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
+#define SPI_NOR_HAS_BPNV BIT(16) /* Block protection bits can be set
+ * volatile, meaning all blocks
+ * are protected by default at reset
+ * (BP[0-2] reset to 1 at power up)
+ */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
@@ -1345,6 +1350,43 @@ static int stm_is_locked(struct spi_nor *nor, loff_t ofs, uint64_t len)
return stm_is_locked_sr(nor, ofs, len, status);
}
+static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr);
+
+static int spi_nor_set_powerup_lock(struct mtd_info *mtd)
+{
+ struct spi_nor *nor = mtd_to_spi_nor(mtd);
+ struct device *dev = nor->dev;
+ u8 sr_cr[2];
+ int ret;
+
+ ret = read_cr(nor);
+ if (ret < 0) {
+ dev_err(dev, "error while reading configuration register\n");
+ return -EINVAL;
+ }
+
+ if (ret & CR_BPNV)
+ return 0;
+
+ sr_cr[1] = ret | CR_BPNV;
+
+ /* Keep the current value of the Status Register. */
+ ret = read_sr(nor);
+ if (ret < 0) {
+ dev_err(dev, "error while reading status register\n");
+ return -EINVAL;
+ }
+ sr_cr[0] = ret;
+
+ ret = write_sr_cr(nor, sr_cr);
+ if (ret)
+ return ret;
+
+ mtd->flags |= MTD_POWERUP_LOCK;
+
+ return 0;
+}
+
static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
@@ -1903,7 +1945,8 @@ static const struct flash_info spi_nor_ids[] = {
{ "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256,
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | USE_CLSR) },
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB |
+ SPI_NOR_HAS_BPNV | USE_CLSR) },
{ "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
@@ -4074,6 +4117,18 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->_is_locked = spi_nor_is_locked;
}
+ if (info->flags & SPI_NOR_HAS_BPNV) {
+ mtd->_set_powerup_lock = spi_nor_set_powerup_lock;
+
+ ret = read_cr(nor);
+ if (ret >= 0) {
+ if (ret & CR_BPNV)
+ mtd->flags |= MTD_POWERUP_LOCK;
+ } else {
+ dev_err(dev, "error reading configuration register\n");
+ }
+ }
+
/* sst nor chips use AAI word program */
if (info->flags & SST_WRITE)
mtd->_write = sst_write;
@@ -313,6 +313,7 @@ struct mtd_info {
int (*_writev) (struct mtd_info *mtd, const struct kvec *vecs,
unsigned long count, loff_t to, size_t *retlen);
void (*_sync) (struct mtd_info *mtd);
+ int (*_set_powerup_lock) (struct mtd_info *mtd);
int (*_lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
int (*_unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
int (*_is_locked) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
@@ -451,6 +452,7 @@ static inline void mtd_sync(struct mtd_info *mtd)
int mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
int mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
int mtd_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
+int mtd_set_powerup_lock(struct mtd_info *mtd);
int mtd_block_isreserved(struct mtd_info *mtd, loff_t ofs);
int mtd_block_isbad(struct mtd_info *mtd, loff_t ofs);
int mtd_block_markbad(struct mtd_info *mtd, loff_t ofs);
@@ -144,6 +144,7 @@
#define FSR_PT_ERR BIT(1) /* Protection error bit */
/* Configuration Register bits. */
+#define CR_BPNV BIT(3) /* Block protection non-volatile */
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
/* Status Register 2 bits. */
@@ -204,6 +204,10 @@ struct otp_info {
* without OOB, e.g., NOR flash.
*/
#define MEMWRITE _IOWR('M', 24, struct mtd_write_req)
+/* Set device to revert to locked state at reset; NB, on some devices this
+ * is an OTP bit so this setting may be irreversible
+ */
+#define MEMSETPOWERUPLOCK _IO('M', 25)
/*
* Obsolete legacy interface. Keep it in order not to break userspace
Setting the BPNV bit forces the block protection bits BP0-2 to 1 at reset. This means that all the flash sectors are protected until they are explicitly unlocked by the user. Together with protection of the status register via the SRWD bit and the WP# signal, this allows a flash device to be effectively protected from erasure by unauthorized actors. NB: the BPNV bit is an OTP bit so this setting is irreversible. Tested with a Cypress s25fl512s. Signed-off-by: Jonas Bonn <jonas@norrbonn.se> --- drivers/mtd/mtdchar.c | 6 ++++ drivers/mtd/mtdcore.c | 8 +++++ drivers/mtd/spi-nor/spi-nor.c | 59 +++++++++++++++++++++++++++++++++-- include/linux/mtd/mtd.h | 2 ++ include/linux/mtd/spi-nor.h | 1 + include/uapi/mtd/mtd-abi.h | 4 +++ 6 files changed, 78 insertions(+), 2 deletions(-)