| Message ID | 20181212163057.22183-1-tudor.ambarus@microchip.com |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [1/2] ARM: dts: at91: at91-sama5d27_som1: add QSPI1 + SPI NOR memory nodes | expand |
On 12/12/2018 16:31:08+0000, Tudor.Ambarus@microchip.com wrote: > From: Claudiu Beznea <claudiu.beznea@microchip.com> > > Configure the QSPI1 controller pin muxing and declare the > jedec,spi-nor memory (SST26VF064). > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > [tudor.ambarus@microchip.com: add spi-rx/tx-bus-width, drop partitions, > reword commit.] > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- > arch/arm/boot/dts/at91-sama5d27_som1.dtsi | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > Applied, thanks.
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi index cf0087b4c9e1..33a159c0163f 100644 --- a/arch/arm/boot/dts/at91-sama5d27_som1.dtsi +++ b/arch/arm/boot/dts/at91-sama5d27_som1.dtsi @@ -62,6 +62,20 @@ ahb { apb { + qspi1: spi@f0024000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; + }; + macb0: ethernet@f8008000 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_default>; @@ -78,6 +92,22 @@ pinctrl@fc038000 { + pinctrl_qspi1_default: qspi1_default { + sck_cs { + pinmux = <PIN_PB5__QSPI1_SCK>, + <PIN_PB6__QSPI1_CS>; + bias-disable; + }; + + data { + pinmux = <PIN_PB7__QSPI1_IO0>, + <PIN_PB8__QSPI1_IO1>, + <PIN_PB9__QSPI1_IO2>, + <PIN_PB10__QSPI1_IO3>; + bias-pull-up; + }; + }; + pinctrl_macb0_default: macb0_default { pinmux = <PIN_PD9__GTXCK>, <PIN_PD10__GTXEN>,