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[178.118.196.9]) by smtp.gmail.com with ESMTPSA id e64sm1834235wmg.22.2018.04.20.01.26.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Apr 2018 01:26:18 -0700 (PDT) From: Sam Lefebvre To: linux-mtd@lists.infradead.org Subject: [PATCH 16/18] mtd: rawnand: gpmi: inline gpmi_cmd_ctrl() Date: Fri, 20 Apr 2018 10:19:44 +0200 Message-Id: <20180420081946.16088-17-sam.lefebvre@essensium.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180420081946.16088-1-sam.lefebvre@essensium.com> References: <20180420081946.16088-1-sam.lefebvre@essensium.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180420_012632_247205_A26E5868 X-CRM114-Status: GOOD ( 17.86 ) X-Spam-Score: 1.0 (+) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (1.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [2a00:1450:400c:c0c:0:0:0:241 listed in] [list.dnswl.org] 1.0 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 T_DKIMWL_WL_MED DKIMwl.org - Whitelisted Medium sender X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Han Xu , Sam Lefebvre , "Arnout Vandecappelle \(Essensium/Mind\)" MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: "Arnout Vandecappelle (Essensium/Mind)" gpmi_cmd_ctrl() has two "states": * ALE or CLE is set, in this case the command/control data is buffered. These calls are replaced with this->cmd_buffer[this->command_length++] = data; * ALE and CLE are not set, in this case the command is sent (DMA is started). These calls are replaced with ret = gpmi_send_command(this); if (ret) dev_err(this->dev, "Chip: %u, Error %d\n", this->current_chip, ret); this->command_length = 0; The 'ctrl' variable/parameter is not used. Signed-off-by: Arnout Vandecappelle (Essensium/Mind) --- drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 85 ++++++++++-------------------- 1 file changed, 29 insertions(+), 56 deletions(-) diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c index 5700ca1d2ae6..97d44fe212c9 100644 --- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c @@ -786,40 +786,6 @@ static int gpmi_alloc_dma_buffer(struct gpmi_nand_data *this) return -ENOMEM; } -static void gpmi_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) -{ - struct nand_chip *chip = mtd_to_nand(mtd); - struct gpmi_nand_data *this = nand_get_controller_data(chip); - int ret; - - /* - * Every operation begins with a command byte and a series of zero or - * more address bytes. These are distinguished by either the Address - * Latch Enable (ALE) or Command Latch Enable (CLE) signals being - * asserted. When MTD is ready to execute the command, it will deassert - * both latch enables. - * - * Rather than run a separate DMA operation for every single byte, we - * queue them up and run a single DMA operation for the entire series - * of command and data bytes. NAND_CMD_NONE means the END of the queue. - */ - if ((ctrl & (NAND_ALE | NAND_CLE))) { - if (data != NAND_CMD_NONE) - this->cmd_buffer[this->command_length++] = data; - return; - } - - if (!this->command_length) - return; - - ret = gpmi_send_command(this); - if (ret) - dev_err(this->dev, "Chip: %u, Error %d\n", - this->current_chip, ret); - - this->command_length = 0; -} - static int gpmi_dev_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd_to_nand(mtd); @@ -1104,7 +1070,8 @@ static void gpmi_nand_command(struct mtd_info *mtd, unsigned int command, int column, int page_addr) { register struct nand_chip *chip = mtd_to_nand(mtd); - int ctrl = NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE; + struct gpmi_nand_data *this = nand_get_controller_data(chip); + int ret; /* Large page devices (> 512 bytes) behave slightly differently. */ bool is_lp = mtd->writesize > 512; @@ -1132,39 +1099,41 @@ static void gpmi_nand_command(struct mtd_info *mtd, unsigned int command, column -= 256; readcmd = NAND_CMD_READ1; } - gpmi_cmd_ctrl(mtd, readcmd, ctrl); - ctrl &= ~NAND_CTRL_CHANGE; + this->cmd_buffer[this->command_length++] = readcmd; } /* Command latch cycle */ if (command != NAND_CMD_NONE) - gpmi_cmd_ctrl(mtd, command, ctrl); + this->cmd_buffer[this->command_length++] = command; - /* Address cycle, when necessary */ - ctrl = NAND_NCE | NAND_ALE | NAND_CTRL_CHANGE; /* Serially input address */ if (column != -1) { /* Adjust columns for 16 bit buswidth */ if (chip->options & NAND_BUSWIDTH_16 && !nand_opcode_8bits(command)) column >>= 1; - gpmi_cmd_ctrl(mtd, column, ctrl); - ctrl &= ~NAND_CTRL_CHANGE; + this->cmd_buffer[this->command_length++] = column; /* Only output a single addr cycle for 8bits opcodes. */ if (is_lp && !nand_opcode_8bits(command)) - gpmi_cmd_ctrl(mtd, column >> 8, ctrl); + this->cmd_buffer[this->command_length++] = column >> 8; } if (page_addr != -1) { - gpmi_cmd_ctrl(mtd, page_addr, ctrl); - ctrl &= ~NAND_CTRL_CHANGE; - gpmi_cmd_ctrl(mtd, page_addr >> 8, ctrl); + this->cmd_buffer[this->command_length++] = page_addr; + this->cmd_buffer[this->command_length++] = page_addr >> 8; if (chip->options & NAND_ROW_ADDR_3) - gpmi_cmd_ctrl(mtd, page_addr >> 16, ctrl); + this->cmd_buffer[this->command_length++] = page_addr >> 16; } /* This starts the DMA for the command and waits for it to finish. */ - gpmi_cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + if (this->command_length > 0) { + ret = gpmi_send_command(this); + if (ret) + dev_err(this->dev, "Chip: %u, Error %d\n", + this->current_chip, ret); + + this->command_length = 0; + } if (!is_lp) return; @@ -1172,10 +1141,12 @@ static void gpmi_nand_command(struct mtd_info *mtd, unsigned int command, switch (command) { case NAND_CMD_RNDOUT: /* No ready / busy check necessary */ - gpmi_cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART, - NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); - gpmi_cmd_ctrl(mtd, NAND_CMD_NONE, - NAND_NCE | NAND_CTRL_CHANGE); + this->cmd_buffer[this->command_length++] = NAND_CMD_RNDOUTSTART; + ret = gpmi_send_command(this); + if (ret) + dev_err(this->dev, "Chip: %u, Error %d\n", + this->current_chip, ret); + this->command_length = 0; break; case NAND_CMD_READ0: @@ -1188,10 +1159,12 @@ static void gpmi_nand_command(struct mtd_info *mtd, unsigned int command, if (column == -1 && page_addr == -1) return; - gpmi_cmd_ctrl(mtd, NAND_CMD_READSTART, - NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE); - gpmi_cmd_ctrl(mtd, NAND_CMD_NONE, - NAND_NCE | NAND_CTRL_CHANGE); + this->cmd_buffer[this->command_length++] = NAND_CMD_READSTART; + ret = gpmi_send_command(this); + if (ret) + dev_err(this->dev, "Chip: %u, Error %d\n", + this->current_chip, ret); + this->command_length = 0; break; } }