From patchwork Thu Sep 24 12:24:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yicong Yang X-Patchwork-Id: 1370657 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2001:8b0:10b:1231::1; helo=merlin.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=merlin.20170209 header.b=T7Tab6Xb; dkim-atps=neutral Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:8b0:10b:1231::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BxvSH0X2nz9sTg for ; Thu, 24 Sep 2020 22:27:11 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=RQtsb5kMweKqNq47shF/4ciDHiDJbB8XfYRgX3X5B54=; b=T7Tab6XbdJhm8tpjW+ELEMfnV y+UvE2Tr0cI9p1TNdpShRKh51pGItgCnX4/oVg9u51HiWqwaPu3rU4sR/5qZd0bXmhOcdRZuntQxG yohiv5iRBd3lqq13ksBLYqGWnU0iI0/p1zpplJhuzkfv5l+kEDnSYy2WaGDWBnEcmey6OXVIlNw0x 1mE9QAlw+Ka+0I3s7c1Fs9Q8eQOyY9Z7OByGeHlfbh8vnXGjF+CrhQHr3rh5/Y7hN29QQ2x8+xGiN IM7gmY51W+2uI0YWL6xKw11IMTIh2OFhTx27h4m+xD+HgUJ4c79XoYJuszXf24zpAXsLjZhKZe10S elrbZy8cg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLQKB-0007S6-9m; Thu, 24 Sep 2020 12:26:11 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kLQK2-0007Oa-I7 for linux-mtd@lists.infradead.org; Thu, 24 Sep 2020 12:26:03 +0000 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 455BBEEFC9594D316F69; Thu, 24 Sep 2020 20:25:53 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.487.0; Thu, 24 Sep 2020 20:25:46 +0800 From: Yicong Yang To: , Subject: [PATCH 3/4] spi: hisi-sfc-v3xx: factor out the bit definition of interrupt register Date: Thu, 24 Sep 2020 20:24:29 +0800 Message-ID: <1600950270-52536-4-git-send-email-yangyicong@hisilicon.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1600950270-52536-1-git-send-email-yangyicong@hisilicon.com> References: <1600950270-52536-1-git-send-email-yangyicong@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200924_082602_853479_D803B5D5 X-CRM114-Status: GOOD ( 11.33 ) X-Spam-Score: -2.1 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.1 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.32 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.32 listed in wl.mailspike.net] 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-spi@vger.kernel.org, linux-mtd@lists.infradead.org, yangyicong@hisilicon.com, tudor.ambarus@microchip.com Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The definition of the register field in the interrupt corresponding registers are the same. So factor them out to public place. Acked-by: John Garry Signed-off-by: Yicong Yang --- drivers/spi/spi-hisi-sfc-v3xx.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-hisi-sfc-v3xx.c b/drivers/spi/spi-hisi-sfc-v3xx.c index 62d4ed8..4a241d7 100644 --- a/drivers/spi/spi-hisi-sfc-v3xx.c +++ b/drivers/spi/spi-hisi-sfc-v3xx.c @@ -18,10 +18,7 @@ #define HISI_SFC_V3XX_VERSION (0x1f8) #define HISI_SFC_V3XX_INT_STAT (0x120) -#define HISI_SFC_V3XX_INT_STAT_PP_ERR BIT(2) -#define HISI_SFC_V3XX_INT_STAT_ADDR_IACCES BIT(5) #define HISI_SFC_V3XX_INT_CLR (0x12c) -#define HISI_SFC_V3XX_INT_CLR_CLEAR (0xff) #define HISI_SFC_V3XX_CMD_CFG (0x300) #define HISI_SFC_V3XX_CMD_CFG_DATA_CNT_OFF 9 #define HISI_SFC_V3XX_CMD_CFG_RW_MSK BIT(8) @@ -34,6 +31,13 @@ #define HISI_SFC_V3XX_CMD_ADDR (0x30c) #define HISI_SFC_V3XX_CMD_DATABUF0 (0x400) +/* Common definition of interrupt bit masks */ +#define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff) /* all the masks */ +#define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2) /* page progrom error */ +#define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5) /* error visiting inaccessible/ + * protected address + */ + /* IO Mode definition in HISI_SFC_V3XX_CMD_CFG */ #define HISI_SFC_V3XX_STD (0 << 17) #define HISI_SFC_V3XX_DIDO (1 << 17) @@ -266,15 +270,15 @@ static int hisi_sfc_v3xx_generic_exec_op(struct hisi_sfc_v3xx_host *host, * next time judgement. */ int_stat = readl(host->regbase + HISI_SFC_V3XX_INT_STAT); - writel(HISI_SFC_V3XX_INT_CLR_CLEAR, + writel(HISI_SFC_V3XX_INT_MASK_ALL, host->regbase + HISI_SFC_V3XX_INT_CLR); - if (int_stat & HISI_SFC_V3XX_INT_STAT_ADDR_IACCES) { + if (int_stat & HISI_SFC_V3XX_INT_MASK_IACCES) { dev_err(host->dev, "fail to access protected address\n"); return -EIO; } - if (int_stat & HISI_SFC_V3XX_INT_STAT_PP_ERR) { + if (int_stat & HISI_SFC_V3XX_INT_MASK_PP_ERR) { dev_err(host->dev, "page program operation failed\n"); return -EIO; }