| Message ID | 1587103677-244754-1-git-send-email-chenxiang66@hisilicon.com |
|---|---|
| State | Accepted |
| Delegated to: | Ambarus Tudor |
| Headers | show |
| Series | [v2] mtd: spi-nor: Enable locking for n25q128a11 | expand |
On Friday, April 17, 2020 9:07:57 AM EEST chenxiang wrote: > From: Xiang Chen <chenxiang66@hisilicon.com> > > As 4bit block protection patchset for some micron models are merged, > n25q128a11 also uses 4 bit Block Protection scheme, so enable locking > for it. Tested it on n25q128a11, the locking functions work well. > > Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> > Reviewed-by: Jungseung Lee <js07.lee@samsung.com> > --- > drivers/mtd/spi-nor/micron-st.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Added Shreyas' T-b tag and applied, thanks!
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 6c034b9..02c0b53 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -29,7 +29,9 @@ static const struct flash_info st_parts[] = { { "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | + SPI_NOR_4BIT_BP | SPI_NOR_BP3_SR_BIT6) }, { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,