| Message ID | 1490979724-10905-2-git-send-email-ludovic.Barre@st.com |
|---|---|
| State | Superseded |
| Delegated to: | Cyrille Pitchen |
| Headers | show |
On Fri, Mar 31, 2017 at 07:02:03PM +0200, Ludovic Barre wrote: > From: Ludovic Barre <ludovic.barre@st.com> > > This patch adds documentation of device tree bindings for the STM32 > QSPI controller. > > Signed-off-by: Ludovic Barre <ludovic.barre@st.com> > --- > .../devicetree/bindings/mtd/stm32-quadspi.txt | 45 ++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mtd/stm32-quadspi.txt > > diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt > new file mode 100644 > index 0000000..95a8ebd > --- /dev/null > +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt > @@ -0,0 +1,45 @@ > +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) > + > +Required properties: > +- compatible: should be "st,stm32f469-qspi" > +- reg: contains the register location and length. > + (optional) the memory mapping address and length Why optional? Either the h/w has it or doesn't. If some chips don't, they should have a different compatible string. > +- reg-names: list of the names corresponding to the previous register > + Should contain "qspi" to register location > + (optional) "qspi_mm" if read in memory map mode (improve read throughput) > +- interrupts: should contain the interrupt for the device > +- clocks: the phandle of the clock needed by the QSPI controller > +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer > + > +Optional properties: > +- resets: must contain the phandle to the reset controller. > + > +A spi flash must be a child of the nor_flash node and could have some > +properties. Also see jedec,spi-nor.txt. > + > +Required properties: > +- reg: chip-Select number (QSPI controller may connect 2 nor flashes) > +- spi-max-frequency: max frequency of spi bus > + > +Optional property: > +- spi-rx-bus-width: the bus width (number of data wires) Just "see ../spi/spi-bus.txt" for the description > + > +Example: > + > +qspi: qspi@a0001000 { spi@... > + compatible = "st,stm32f469-qspi"; > + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; > + reg-names = "qspi", "qspi_mm"; > + interrupts = <91>; > + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; > + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_qspi0>; > + > + flash@0 { > + reg = <0>; > + spi-rx-bus-width = <4>; > + spi-max-frequency = <108000000>; > + ... > + }; > +}; > -- > 2.7.4 >
Hi Rob thanks for review my comments below br Ludo On 04/03/2017 06:57 PM, Rob Herring wrote: > On Fri, Mar 31, 2017 at 07:02:03PM +0200, Ludovic Barre wrote: >> From: Ludovic Barre <ludovic.barre@st.com> >> >> This patch adds documentation of device tree bindings for the STM32 >> QSPI controller. >> >> Signed-off-by: Ludovic Barre <ludovic.barre@st.com> >> --- >> .../devicetree/bindings/mtd/stm32-quadspi.txt | 45 ++++++++++++++++++++++ >> 1 file changed, 45 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >> >> diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >> new file mode 100644 >> index 0000000..95a8ebd >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >> @@ -0,0 +1,45 @@ >> +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) >> + >> +Required properties: >> +- compatible: should be "st,stm32f469-qspi" >> +- reg: contains the register location and length. >> + (optional) the memory mapping address and length > Why optional? Either the h/w has it or doesn't. If some chips don't, > they should have a different compatible string. in fact, the stm32 qspi controller can operate in any of the following modes: -indirect mode: all the operations are performed using the qspi registers with read/write. -read memory-mapped mode: the external Flash memory is mapped to the microcontroller address space and is seen by the system as if it was an internal memory (use memcpy_fromio). this mode improve read throughput if qspi_mm is defined the qspi controller use read memory-mapped mode else the controller transfers in indirect mode. >> +- reg-names: list of the names corresponding to the previous register >> + Should contain "qspi" to register location >> + (optional) "qspi_mm" if read in memory map mode (improve read throughput) >> +- interrupts: should contain the interrupt for the device >> +- clocks: the phandle of the clock needed by the QSPI controller >> +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer >> + >> +Optional properties: >> +- resets: must contain the phandle to the reset controller. >> + >> +A spi flash must be a child of the nor_flash node and could have some >> +properties. Also see jedec,spi-nor.txt. >> + >> +Required properties: >> +- reg: chip-Select number (QSPI controller may connect 2 nor flashes) >> +- spi-max-frequency: max frequency of spi bus >> + >> +Optional property: >> +- spi-rx-bus-width: the bus width (number of data wires) > Just "see ../spi/spi-bus.txt" for the description ok > >> + >> +Example: >> + >> +qspi: qspi@a0001000 { > spi@... ok >> + compatible = "st,stm32f469-qspi"; >> + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; >> + reg-names = "qspi", "qspi_mm"; >> + interrupts = <91>; >> + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; >> + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_qspi0>; >> + >> + flash@0 { >> + reg = <0>; >> + spi-rx-bus-width = <4>; >> + spi-max-frequency = <108000000>; >> + ... >> + }; >> +}; >> -- >> 2.7.4 >>
On Tue, Apr 4, 2017 at 2:28 AM, Ludovic BARRE <ludovic.barre@st.com> wrote: > Hi Rob > > thanks for review > my comments below > > br > Ludo > > On 04/03/2017 06:57 PM, Rob Herring wrote: >> >> On Fri, Mar 31, 2017 at 07:02:03PM +0200, Ludovic Barre wrote: >>> >>> From: Ludovic Barre <ludovic.barre@st.com> >>> >>> This patch adds documentation of device tree bindings for the STM32 >>> QSPI controller. >>> >>> Signed-off-by: Ludovic Barre <ludovic.barre@st.com> >>> --- >>> .../devicetree/bindings/mtd/stm32-quadspi.txt | 45 >>> ++++++++++++++++++++++ >>> 1 file changed, 45 insertions(+) >>> create mode 100644 >>> Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >>> >>> diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >>> b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >>> new file mode 100644 >>> index 0000000..95a8ebd >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >>> @@ -0,0 +1,45 @@ >>> +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) >>> + >>> +Required properties: >>> +- compatible: should be "st,stm32f469-qspi" >>> +- reg: contains the register location and length. >>> + (optional) the memory mapping address and length >> >> Why optional? Either the h/w has it or doesn't. If some chips don't, >> they should have a different compatible string. > > in fact, the stm32 qspi controller can operate in any of the following > modes: > -indirect mode: all the operations are performed using the qspi registers > with read/write. > -read memory-mapped mode: the external Flash memory is mapped to the > microcontroller address space and is seen by the system as if it was > an internal memory (use memcpy_fromio). this mode improve read throughput > > if qspi_mm is defined the qspi controller use read memory-mapped mode > else the controller transfers in indirect mode. You should always have the memory region defined because that's what the h/w has. If you want another property to select the mode, then perhaps that's fine. But why? Can't the OS figure out which to use? Why would you ever not use memory mapped mode unless the driver doesn't yet support it? Rob
On 04/04/2017 02:20 PM, Rob Herring wrote: > On Tue, Apr 4, 2017 at 2:28 AM, Ludovic BARRE <ludovic.barre@st.com> wrote: >> Hi Rob >> >> thanks for review >> my comments below >> >> br >> Ludo >> >> On 04/03/2017 06:57 PM, Rob Herring wrote: >>> On Fri, Mar 31, 2017 at 07:02:03PM +0200, Ludovic Barre wrote: >>>> From: Ludovic Barre <ludovic.barre@st.com> >>>> >>>> This patch adds documentation of device tree bindings for the STM32 >>>> QSPI controller. >>>> >>>> Signed-off-by: Ludovic Barre <ludovic.barre@st.com> >>>> --- >>>> .../devicetree/bindings/mtd/stm32-quadspi.txt | 45 >>>> ++++++++++++++++++++++ >>>> 1 file changed, 45 insertions(+) >>>> create mode 100644 >>>> Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >>>> >>>> diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >>>> b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >>>> new file mode 100644 >>>> index 0000000..95a8ebd >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt >>>> @@ -0,0 +1,45 @@ >>>> +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) >>>> + >>>> +Required properties: >>>> +- compatible: should be "st,stm32f469-qspi" >>>> +- reg: contains the register location and length. >>>> + (optional) the memory mapping address and length >>> Why optional? Either the h/w has it or doesn't. If some chips don't, >>> they should have a different compatible string. >> in fact, the stm32 qspi controller can operate in any of the following >> modes: >> -indirect mode: all the operations are performed using the qspi registers >> with read/write. >> -read memory-mapped mode: the external Flash memory is mapped to the >> microcontroller address space and is seen by the system as if it was >> an internal memory (use memcpy_fromio). this mode improve read throughput >> >> if qspi_mm is defined the qspi controller use read memory-mapped mode >> else the controller transfers in indirect mode. > You should always have the memory region defined because that's what > the h/w has. If you want another property to select the mode, then > perhaps that's fine. But why? Can't the OS figure out which to use? > Why would you ever not use memory mapped mode unless the driver > doesn't yet support it? ok, I always map the memory region (qspi_mm is now required). if the nor-flash is more bigger than "qspi memory region", I force to use the indirect mode. > Rob
diff --git a/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt new file mode 100644 index 0000000..95a8ebd --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/stm32-quadspi.txt @@ -0,0 +1,45 @@ +* STMicroelectronics Quad Serial Peripheral Interface(QuadSPI) + +Required properties: +- compatible: should be "st,stm32f469-qspi" +- reg: contains the register location and length. + (optional) the memory mapping address and length +- reg-names: list of the names corresponding to the previous register + Should contain "qspi" to register location + (optional) "qspi_mm" if read in memory map mode (improve read throughput) +- interrupts: should contain the interrupt for the device +- clocks: the phandle of the clock needed by the QSPI controller +- A pinctrl must be defined to set pins in mode of operation for QSPI transfer + +Optional properties: +- resets: must contain the phandle to the reset controller. + +A spi flash must be a child of the nor_flash node and could have some +properties. Also see jedec,spi-nor.txt. + +Required properties: +- reg: chip-Select number (QSPI controller may connect 2 nor flashes) +- spi-max-frequency: max frequency of spi bus + +Optional property: +- spi-rx-bus-width: the bus width (number of data wires) + +Example: + +qspi: qspi@a0001000 { + compatible = "st,stm32f469-qspi"; + reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = <91>; + resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0>; + + flash@0 { + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + ... + }; +};