From patchwork Thu Mar 23 09:43:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UGV0ZXIgUGFuIOa9mOagiyAocGV0ZXJwYW5kb25nKQ==?= X-Patchwork-Id: 742577 X-Patchwork-Delegate: boris.brezillon@free-electrons.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vphH65RqQz9s2s for ; Thu, 23 Mar 2017 20:35:14 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="UIobfka6"; dkim-atps=neutral DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 23 Mar 2017 03:32:18 -0600 Received: from bowex17d.micron.com (137.201.21.212) by SIWEX5B.sing.micron.com (10.160.29.60) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Thu, 23 Mar 2017 17:32:13 +0800 Received: from peterpan-Linux-Desktop.micron.com (10.66.12.56) by bowex17d.micron.com (137.201.21.212) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Thu, 23 Mar 2017 03:32:11 -0600 From: Peter Pan To: , , , , , , , Subject: [PATCH v4 8/9] nand: spi: Add generic SPI controller support Date: Thu, 23 Mar 2017 17:43:45 +0800 Message-ID: <1490262226-29092-9-git-send-email-peterpandong@micron.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1490262226-29092-1-git-send-email-peterpandong@micron.com> References: <1490262226-29092-1-git-send-email-peterpandong@micron.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-12.0.0.1464-8.100.1062-22958.004 X-TM-AS-Result: No--3.369200-0.000000-31 X-TM-AS-MatchedID: 150215-702358-105640-860493-863432-862883-703529-188019-7 08712-704496-704425-700324-860275-702796-113670-703786-703352-711219-702020 -705102-702067-703275-703468-114012-700648-703523-700918-700811-300010-7074 51-706290-701775-700476-851458-704421-186003-121665-704713-705753-704318-10 5630-106420-708060-704287-704568-703969-121336-148004-148036-42000-42003-52 000 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-MT-CheckInternalSenderRule: True X-Scanned-By: MIMEDefang 2.78 on 137.201.130.65 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170323_023415_148439_FCAB5C4D X-CRM114-Status: GOOD ( 17.11 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [137.201.242.129 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peterpansjtu@gmail.com, linshunquan1@hisilicon.com, peterpandong@micron.com Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This commit supports to use generic spi controller as spi nand controller. Signed-off-by: Peter Pan --- drivers/mtd/nand/spi/Kconfig | 2 + drivers/mtd/nand/spi/Makefile | 1 + drivers/mtd/nand/spi/controllers/Kconfig | 5 + drivers/mtd/nand/spi/controllers/Makefile | 1 + drivers/mtd/nand/spi/controllers/generic-spi.c | 150 +++++++++++++++++++++++++ 5 files changed, 159 insertions(+) create mode 100644 drivers/mtd/nand/spi/controllers/Kconfig create mode 100644 drivers/mtd/nand/spi/controllers/Makefile create mode 100644 drivers/mtd/nand/spi/controllers/generic-spi.c diff --git a/drivers/mtd/nand/spi/Kconfig b/drivers/mtd/nand/spi/Kconfig index d77c46e..6bd1c65 100644 --- a/drivers/mtd/nand/spi/Kconfig +++ b/drivers/mtd/nand/spi/Kconfig @@ -3,3 +3,5 @@ menuconfig MTD_SPI_NAND depends on MTD_NAND help This is the framework for the SPI NAND device drivers. + +source "drivers/mtd/nand/spi/controllers/Kconfig" diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile index db0b91b..6ad5f24 100644 --- a/drivers/mtd/nand/spi/Makefile +++ b/drivers/mtd/nand/spi/Makefile @@ -1,3 +1,4 @@ obj-$(CONFIG_MTD_SPI_NAND) += core.o obj-$(CONFIG_MTD_SPI_NAND) += manufactures.o obj-$(CONFIG_MTD_SPI_NAND) += micron.o +obj-$(CONFIG_MTD_SPI_NAND) += controllers/ diff --git a/drivers/mtd/nand/spi/controllers/Kconfig b/drivers/mtd/nand/spi/controllers/Kconfig new file mode 100644 index 0000000..8ab7023 --- /dev/null +++ b/drivers/mtd/nand/spi/controllers/Kconfig @@ -0,0 +1,5 @@ +config GENERIC_SPI_NAND + tristate "SPI NAND with generic SPI bus Support" + depends on MTD_SPI_NAND && SPI + help + This is to support SPI NAND device with generic SPI bus. diff --git a/drivers/mtd/nand/spi/controllers/Makefile b/drivers/mtd/nand/spi/controllers/Makefile new file mode 100644 index 0000000..46cbf29 --- /dev/null +++ b/drivers/mtd/nand/spi/controllers/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_GENERIC_SPI_NAND) += generic-spi.o diff --git a/drivers/mtd/nand/spi/controllers/generic-spi.c b/drivers/mtd/nand/spi/controllers/generic-spi.c new file mode 100644 index 0000000..da1f224 --- /dev/null +++ b/drivers/mtd/nand/spi/controllers/generic-spi.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2009-2017 Micron Technology, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include +#include +#include +#include + +struct gen_spi_spinand_controller { + struct spinand_controller ctrl; + struct spi_device *spi; +}; + +#define to_gen_spi_spinand_controller(c) \ + container_of(c, struct gen_spi_spinand_controller, ctrl) + +/* + * gen_spi_spinand_exec_op - to process a command to send to the + * SPI NAND by generic SPI bus + * @chip: SPI NAND device structure + * @op: SPI NAND operation descriptor + */ +static int gen_spi_spinand_exec_op(struct spinand_device *chip, + struct spinand_op *op) +{ + struct spi_message message; + struct spi_transfer x[3]; + struct spinand_controller *scontroller = chip->controller.controller; + struct gen_spi_spinand_controller *controller; + + controller = to_gen_spi_spinand_controller(scontroller); + spi_message_init(&message); + memset(x, 0, sizeof(x)); + x[0].len = 1; + x[0].tx_nbits = 1; + x[0].tx_buf = &op->cmd; + spi_message_add_tail(&x[0], &message); + + if (op->n_addr + op->dummy_bytes) { + x[1].len = op->n_addr + op->dummy_bytes; + x[1].tx_nbits = op->addr_nbits; + x[1].tx_buf = op->addr; + spi_message_add_tail(&x[1], &message); + } + if (op->n_tx) { + x[2].len = op->n_tx; + x[2].tx_nbits = op->data_nbits; + x[2].tx_buf = op->tx_buf; + spi_message_add_tail(&x[2], &message); + } else if (op->n_rx) { + x[2].len = op->n_rx; + x[2].rx_nbits = op->data_nbits; + x[2].rx_buf = op->rx_buf; + spi_message_add_tail(&x[2], &message); + } + return spi_sync(controller->spi, &message); +} + +static struct spinand_controller_ops gen_spi_spinand_ops = { + .exec_op = gen_spi_spinand_exec_op, +}; + +static int gen_spi_spinand_probe(struct spi_device *spi) +{ + struct spinand_device *chip; + struct gen_spi_spinand_controller *controller; + struct spinand_controller *spinand_controller; + int ret; + u32 max_speed_hz = spi->max_speed_hz; + + chip = spinand_alloc(&spi->dev); + if (IS_ERR(chip)) { + ret = PTR_ERR(chip); + goto err1; + } + controller = kzalloc(sizeof(*controller), GFP_KERNEL); + if (!controller) { + ret = -ENOMEM; + goto err2; + } + controller->spi = spi; + spinand_controller = &controller->ctrl; + spinand_controller->ops = &gen_spi_spinand_ops; + spinand_controller->caps = SPINAND_CAP_RD_X1 | SPINAND_CAP_WR_X1; + if (spi->mode & SPI_RX_QUAD) + spinand_controller->caps |= SPINAND_CAP_RD_QUAD | + SPINAND_CAP_RD_X4; + if (spi->mode & SPI_RX_DUAL) + spinand_controller->caps |= SPINAND_CAP_RD_DUAL | + SPINAND_CAP_RD_X2; + if (spi->mode & SPI_TX_QUAD) + spinand_controller->caps |= SPINAND_CAP_WR_QUAD | + SPINAND_CAP_WR_X4; + if (spi->mode & SPI_TX_DUAL) + spinand_controller->caps |= SPINAND_CAP_WR_DUAL | + SPINAND_CAP_WR_X2; + chip->controller.controller = spinand_controller; + spi_set_drvdata(spi, chip); + spi->max_speed_hz = min_t(int, 25000000, max_speed_hz); + + ret = spinand_register(chip); + if (ret) + goto err3; + + spi->max_speed_hz = max_speed_hz; + + return 0; + +err3: + kfree(controller); +err2: + spinand_free(chip); +err1: + return ret; +} + +static int gen_spi_spinand_remove(struct spi_device *spi) +{ + struct spinand_device *chip = spi_get_drvdata(spi); + + spinand_unregister(chip); + kfree(to_gen_spi_spinand_controller(chip->controller.controller)); + spinand_free(chip); + + return 0; +} + +static struct spi_driver gen_spi_spinand_driver = { + .driver = { + .name = "generic_spinand", + .owner = THIS_MODULE, + }, + .probe = gen_spi_spinand_probe, + .remove = gen_spi_spinand_remove, +}; +module_spi_driver(gen_spi_spinand_driver); + +MODULE_DESCRIPTION("Generic SPI controller to support SPI NAND"); +MODULE_AUTHOR("Peter Pan"); +MODULE_LICENSE("GPL v2");