From patchwork Mon Dec 12 15:40:50 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 705062 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tcnDc2B0Hz9sCG for ; Tue, 13 Dec 2016 02:43:28 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1cGSjw-0002HL-Mt; Mon, 12 Dec 2016 15:42:08 +0000 Received: from 20.mo5.mail-out.ovh.net ([91.121.55.239]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1cGSjr-0002BK-Ts for linux-mtd@lists.infradead.org; Mon, 12 Dec 2016 15:42:05 +0000 Received: from player760.ha.ovh.net (b9.ovh.net [213.186.33.59]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id 1AFCB5525D for ; Mon, 12 Dec 2016 16:41:40 +0100 (CET) Received: from hermes.kaod.org.com (LFbn-1-2234-107.w90-76.abo.wanadoo.fr [90.76.55.107]) (Authenticated sender: clg@kaod.org) by player760.ha.ovh.net (Postfix) with ESMTPSA id 933612F9; Mon, 12 Dec 2016 16:41:27 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: linux-mtd@lists.infradead.org Subject: [PATCH v4 2/4] mtd: aspeed: add memory controllers for the Aspeed AST2400 SoC Date: Mon, 12 Dec 2016 16:40:50 +0100 Message-Id: <1481557252-13656-3-git-send-email-clg@kaod.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1481557252-13656-1-git-send-email-clg@kaod.org> References: <1481557252-13656-1-git-send-email-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 14209982724865559475 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrfeelfedriedvgddvjecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20161212_074204_373234_92AACC5B X-CRM114-Status: GOOD ( 15.27 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [91.121.55.239 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [91.121.55.239 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Boris Brezillon , devicetree@vger.kernel.org, Richard Weinberger , Marek Vasut , Rob Herring , Joel Stanley , Cyrille Pitchen , Brian Norris , David Woodhouse , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This driver adds mtd support for the Aspeed AST2400 SoC static memory controllers: * New Static Memory Controller (referred as FMC) . BMC firmware . AST2500 compatible register set . 5 chip select pins (CE0 ∼ CE4) . supports NOR flash, NAND flash and SPI flash memory. * SPI Flash Controller (SPI) . host Firmware . slightly different register set, between AST2500 and the legacy controller . supports SPI flash memory . 1 chip select pin (CE0) The legacy static memory controller (referred as SMC) is not supported, as well as types other than SPI. Signed-off-by: Cédric Le Goater Reviewed-by: Joel Stanley --- drivers/mtd/spi-nor/Kconfig | 2 +- drivers/mtd/spi-nor/aspeed-smc.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index 42168e9d6097..7b00a0cb9ed8 100644 --- a/drivers/mtd/spi-nor/Kconfig +++ b/drivers/mtd/spi-nor/Kconfig @@ -35,7 +35,7 @@ config SPI_ASPEED_SMC depends on HAS_IOMEM && OF help This enables support for the Firmware Memory controller (FMC) - in the Aspeed AST2500 SoC when attached to SPI NOR chips, + in the Aspeed AST2500/AST2400 SoCs when attached to SPI NOR chips, and support for the SPI flash memory controller (SPI) for the host firmware. The implementation only supports SPI NOR. diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index 2667ab7aeb9b..ce2ab13d114d 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -44,8 +44,27 @@ struct aspeed_smc_info { void (*set_4b)(struct aspeed_smc_chip *chip); }; +static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip); static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip); +static const struct aspeed_smc_info fmc_2400_info = { + .maxsize = 64 * 1024 * 1024, + .nce = 5, + .hastype = true, + .we0 = 16, + .ctl0 = 0x10, + .set_4b = aspeed_smc_chip_set_4b, +}; + +static const struct aspeed_smc_info spi_2400_info = { + .maxsize = 64 * 1024 * 1024, + .nce = 1, + .hastype = false, + .we0 = 0, + .ctl0 = 0x04, + .set_4b = aspeed_smc_chip_set_4b_spi_2400, +}; + static const struct aspeed_smc_info fmc_2500_info = { .maxsize = 256 * 1024 * 1024, .nce = 3, @@ -135,6 +154,7 @@ struct aspeed_smc_controller { #define CONTROL_IO_DUMMY_HI BIT(14) #define CONTROL_IO_DUMMY_HI_SHIFT 14 #define CONTROL_CLK_DIV4 BIT(13) /* others */ +#define CONTROL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI */ #define CONTROL_RW_MERGE BIT(12) #define CONTROL_IO_DUMMY_LO_SHIFT 6 #define CONTROL_IO_DUMMY_LO GENMASK(7, \ @@ -388,6 +408,8 @@ static int aspeed_smc_remove(struct platform_device *dev) } static const struct of_device_id aspeed_smc_matches[] = { + { .compatible = "aspeed,ast2400-fmc", .data = &fmc_2400_info }, + { .compatible = "aspeed,ast2400-spi", .data = &spi_2400_info }, { .compatible = "aspeed,ast2500-fmc", .data = &fmc_2500_info }, { .compatible = "aspeed,ast2500-spi", .data = &spi_2500_info }, { } @@ -461,6 +483,17 @@ static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip) } } +/* + * The AST2400 SPI flash controller does not have a CE Control + * register. It uses the CE0 control register to set 4Byte mode at the + * controller level. + */ +static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip) +{ + chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B; + chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B; +} + static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip, struct resource *res) {