| Message ID | 1475637910-2324-1-git-send-email-nobuhiro.iwamatsu.kw@hitachi.com |
|---|---|
| State | Changes Requested |
| Headers | show |
On Wed, Oct 5, 2016 at 8:55 AM, Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> wrote: > Add Micron N25Q256A13 256Mbit NOR Flash in the list of supported > devices. This chip is the same structure as the N25Q256A but ID > is different. > > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> > --- > > drivers/mtd/spi-nor/spi-nor.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index d0fc165..ce67ccd 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -884,6 +884,7 @@ static const struct flash_info spi_nor_ids[] = { > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, > { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > + { "n25q256a13", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, Since the previous chips follow 'a' notation for bb chips, better to use n25q256a for bb and n25q256 for ba thanks!
On 10/24/2016 10:04 AM, Jagan Teki wrote: > On Wed, Oct 5, 2016 at 8:55 AM, Nobuhiro Iwamatsu > <nobuhiro.iwamatsu.kw@hitachi.com> wrote: >> Add Micron N25Q256A13 256Mbit NOR Flash in the list of supported >> devices. This chip is the same structure as the N25Q256A but ID >> is different. >> >> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> >> --- >> >> drivers/mtd/spi-nor/spi-nor.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c >> index d0fc165..ce67ccd 100644 >> --- a/drivers/mtd/spi-nor/spi-nor.c >> +++ b/drivers/mtd/spi-nor/spi-nor.c >> @@ -884,6 +884,7 @@ static const struct flash_info spi_nor_ids[] = { >> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, >> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, >> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, >> + { "n25q256a13", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, > > Since the previous chips follow 'a' notation for bb chips, better to > use n25q256a for bb and n25q256 for ba Do you mind expanding on this? I don't understand the remark.
On Mon, Oct 24, 2016 at 6:39 PM, Marek Vasut <marek.vasut@gmail.com> wrote: > On 10/24/2016 10:04 AM, Jagan Teki wrote: >> On Wed, Oct 5, 2016 at 8:55 AM, Nobuhiro Iwamatsu >> <nobuhiro.iwamatsu.kw@hitachi.com> wrote: >>> Add Micron N25Q256A13 256Mbit NOR Flash in the list of supported >>> devices. This chip is the same structure as the N25Q256A but ID >>> is different. >>> >>> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> >>> --- >>> >>> drivers/mtd/spi-nor/spi-nor.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c >>> index d0fc165..ce67ccd 100644 >>> --- a/drivers/mtd/spi-nor/spi-nor.c >>> +++ b/drivers/mtd/spi-nor/spi-nor.c >>> @@ -884,6 +884,7 @@ static const struct flash_info spi_nor_ids[] = { >>> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, >>> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, >>> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, >>> + { "n25q256a13", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, >> >> Since the previous chips follow 'a' notation for bb chips, better to >> use n25q256a for bb and n25q256 for ba > > Do you mind expanding on this? I don't understand the remark. { "n25q064", INFO(0x20ba17, { "n25q064a", INFO(0x20bb17, What I am saying is n25q256a is should be n25q256 and the new addition can be n25q256a thanks!
Hi, all. > -----Original Message----- > From: Jagan Teki [mailto:jagan@openedev.com] > Sent: Monday, October 24, 2016 10:21 PM > To: Marek Vasut > Cc: 岩松信洋 / IWAMATSU，NOBUHIRO; linux-mtd@lists.infradead.org; Brian > Norris; 長船辰昭 / OSAFUNE，TATSUAKI; David Woodhouse > Subject: Re: [PATCH] mtd: spi-nor: Add support for N25Q256A13 > > On Mon, Oct 24, 2016 at 6:39 PM, Marek Vasut <marek.vasut@gmail.com> wrote: > > On 10/24/2016 10:04 AM, Jagan Teki wrote: > >> On Wed, Oct 5, 2016 at 8:55 AM, Nobuhiro Iwamatsu > >> <nobuhiro.iwamatsu.kw@hitachi.com> wrote: > >>> Add Micron N25Q256A13 256Mbit NOR Flash in the list of supported > >>> devices. This chip is the same structure as the N25Q256A but ID is > >>> different. > >>> > >>> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> > >>> --- > >>> > >>> drivers/mtd/spi-nor/spi-nor.c | 1 + > >>> 1 file changed, 1 insertion(+) > >>> > >>> diff --git a/drivers/mtd/spi-nor/spi-nor.c > >>> b/drivers/mtd/spi-nor/spi-nor.c index d0fc165..ce67ccd 100644 > >>> --- a/drivers/mtd/spi-nor/spi-nor.c > >>> +++ b/drivers/mtd/spi-nor/spi-nor.c > >>> @@ -884,6 +884,7 @@ static const struct flash_info spi_nor_ids[] = { > >>> { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K > | SPI_NOR_QUAD_READ) }, > >>> { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K > | SPI_NOR_QUAD_READ) }, > >>> { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K > | SPI_NOR_QUAD_READ) }, > >>> + { "n25q256a13", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K > >>> + | SPI_NOR_QUAD_READ) }, > >> > >> Since the previous chips follow 'a' notation for bb chips, better to > >> use n25q256a for bb and n25q256 for ba > > > > Do you mind expanding on this? I don't understand the remark. > > { "n25q064", INFO(0x20ba17, > { "n25q064a", INFO(0x20bb17, > > What I am saying is n25q256a is should be n25q256 and the new addition can > be n25q256a > I see. I will update patch. Thanks! Nobuhiro
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index d0fc165..ce67ccd 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -884,6 +884,7 @@ static const struct flash_info spi_nor_ids[] = { { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { "n25q256a13", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
Add Micron N25Q256A13 256Mbit NOR Flash in the list of supported devices. This chip is the same structure as the N25Q256A but ID is different. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com> --- drivers/mtd/spi-nor/spi-nor.c | 1 + 1 file changed, 1 insertion(+)