From patchwork Mon Aug 15 07:10:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Westerberg X-Patchwork-Id: 659120 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3sCRXP2DZ6z9t1L for ; Mon, 15 Aug 2016 17:12:53 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bZC3L-0004B3-V8; Mon, 15 Aug 2016 07:11:19 +0000 Received: from mga11.intel.com ([192.55.52.93]) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bZC3A-0003pV-Hb for linux-mtd@lists.infradead.org; Mon, 15 Aug 2016 07:11:10 +0000 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP; 15 Aug 2016 00:10:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,524,1464678000"; d="scan'208"; a="1014422499" Received: from black.fi.intel.com ([10.237.72.93]) by orsmga001.jf.intel.com with ESMTP; 15 Aug 2016 00:10:45 -0700 Received: by black.fi.intel.com (Postfix, from userid 1001) id AB6EC34C; Mon, 15 Aug 2016 10:10:44 +0300 (EEST) From: Mika Westerberg To: linux-mtd@lists.infradead.org Subject: [PATCH v3 3/3] mfd: lpc_ich: Add support for Intel Apollo Lake SoC Date: Mon, 15 Aug 2016 10:10:44 +0300 Message-Id: <1471245044-12767-4-git-send-email-mika.westerberg@linux.intel.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1471245044-12767-1-git-send-email-mika.westerberg@linux.intel.com> References: <1471245044-12767-1-git-send-email-mika.westerberg@linux.intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160815_001108_752102_1F6FBBF0 X-CRM114-Status: GOOD ( 13.43 ) X-Spam-Score: -8.3 (--------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-8.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [192.55.52.93 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [192.55.52.93 listed in wl.mailspike.net] -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mika Westerberg , key.seong.lim@intel.com, linux-kernel@vger.kernel.org, Peter Tyser , Brian Norris , Lee Jones , David Woodhouse MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Intel Apollo Lake SoC exposes serial SPI flash through the LPC device. The SPI flash host controller is not discoverable through PCI config cycles because P2SB (function 0 of the device 13) is hidden by the BIOS. We unhide the device briefly in order to read BAR 0 of the SPI host controller. Signed-off-by: Mika Westerberg --- drivers/mfd/lpc_ich.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c index 56a0e98a5f89..b1013b3f4dee 100644 --- a/drivers/mfd/lpc_ich.c +++ b/drivers/mfd/lpc_ich.c @@ -56,6 +56,7 @@ * document number TBD : Wildcat Point-LP * document number TBD : 9 Series * document number TBD : Lewisburg + * document number TBD : Apollo Lake SoC */ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt @@ -92,6 +93,8 @@ #define BCR 0xdc #define BCR_WPD BIT(0) +#define SPIBASE_APL_SZ 4096 + #define GPIOBASE_ICH0 0x58 #define GPIOCTRL_ICH0 0x5C #define GPIOBASE_ICH6 0x48 @@ -239,6 +242,7 @@ enum lpc_chipsets { LPC_BRASWELL, /* Braswell SoC */ LPC_LEWISBURG, /* Lewisburg */ LPC_9S, /* 9 Series */ + LPC_APL, /* Apollo Lake SoC */ }; static struct lpc_ich_info lpc_chipset_info[] = { @@ -559,6 +563,10 @@ static struct lpc_ich_info lpc_chipset_info[] = { .name = "9 Series", .iTCO_version = 2, }, + [LPC_APL] = { + .name = "Apollo Lake SoC", + .spi_type = INTEL_SPI_BXT, + }, }; /* @@ -707,6 +715,7 @@ static const struct pci_device_id lpc_ich_ids[] = { { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, + { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL}, { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, @@ -1122,6 +1131,36 @@ static int lpc_ich_init_spi(struct pci_dev *dev) } break; + case INTEL_SPI_BXT: { + unsigned int p2sb = PCI_DEVFN(13, 0); + unsigned int spi = PCI_DEVFN(13, 2); + struct pci_bus *bus = dev->bus; + + /* + * The P2SB is hidden by BIOS and we need to unhide it in + * order to read BAR of the SPI flash device. Once that is + * done we hide it again. + */ + pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0); + pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0, + &spi_base); + if (spi_base != ~0) { + res->start = spi_base & 0xfffffff0; + res->end = res->start + SPIBASE_APL_SZ - 1; + + pci_bus_read_config_dword(bus, spi, BCR, &bcr); + if (!(bcr & BCR_WPD)) { + bcr |= BCR_WPD; + pci_bus_write_config_dword(bus, spi, BCR, bcr); + pci_bus_read_config_dword(bus, spi, BCR, &bcr); + } + info->writeable = !!(bcr & BCR_WPD); + } + + pci_bus_write_config_byte(dev->bus, p2sb, 0xe1, 0x1); + break; + } + default: return -EINVAL; }