From patchwork Sun Jun 19 16:08:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hauke Mehrtens X-Patchwork-Id: 637710 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3rXf920Gd5z9sxS for ; Mon, 20 Jun 2016 02:10:30 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1bEfHO-0001kg-EU; Sun, 19 Jun 2016 16:08:58 +0000 Received: from hauke-m.de ([2001:41d0:8:b27b::1]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1bEfHB-0001g7-Dd for linux-mtd@lists.infradead.org; Sun, 19 Jun 2016 16:08:47 +0000 Received: from hauke-desktop.lan (p2003008B2F50DB00188C75466EAFB974.dip0.t-ipconnect.de [IPv6:2003:8b:2f50:db00:188c:7546:6eaf:b974]) by hauke-m.de (Postfix) with ESMTPSA id 932C9100064; Sun, 19 Jun 2016 18:08:24 +0200 (CEST) From: Hauke Mehrtens To: boris.brezillon@free-electrons.com, richard@nod.at Subject: [PATCH v3 3/8] MTD: xway: the latched command should be persistent Date: Sun, 19 Jun 2016 18:08:12 +0200 Message-Id: <1466352497-6806-4-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1466352497-6806-1-git-send-email-hauke@hauke-m.de> References: <1466352497-6806-1-git-send-email-hauke@hauke-m.de> X-Spam-Status: No, score=0.0 required=7.0 tests=UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on hauke-m.de X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160619_090845_669109_FEB4803C X-CRM114-Status: GOOD ( 11.38 ) X-Spam-Score: -3.3 (---) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-3.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record -1.4 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-mtd@lists.infradead.org, computersforpeace@gmail.com, dwmw2@infradead.org, Hauke Mehrtens , john@phrozen.org MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: John Crispin With each write the pins on the NAND flash chip have to be activated. Instead of setting them only when NAND_CTRL_CHANGE is given, always set them. Signed-off-by: John Crispin Signed-off-by: Hauke Mehrtens --- drivers/mtd/nand/xway_nand.c | 26 +++++++++++--------------- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c index ec189e5..6028edb 100644 --- a/drivers/mtd/nand/xway_nand.c +++ b/drivers/mtd/nand/xway_nand.c @@ -107,22 +107,18 @@ static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; unsigned long flags; - if (ctrl & NAND_CTRL_CHANGE) { - nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR); - if (ctrl & NAND_CLE) - nandaddr |= NAND_WRITE_CMD; - else - nandaddr |= NAND_WRITE_ADDR; - this->IO_ADDR_W = (void __iomem *) nandaddr; - } + if (cmd == NAND_CMD_NONE) + return; - if (cmd != NAND_CMD_NONE) { - spin_lock_irqsave(&ebu_lock, flags); - writeb(cmd, this->IO_ADDR_W); - while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) - ; - spin_unlock_irqrestore(&ebu_lock, flags); - } + spin_lock_irqsave(&ebu_lock, flags); + if (ctrl & NAND_CLE) + writeb(cmd, (void __iomem *) (nandaddr | NAND_WRITE_CMD)); + else if (ctrl & NAND_ALE) + writeb(cmd, (void __iomem *) (nandaddr | NAND_WRITE_ADDR)); + + while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + spin_unlock_irqrestore(&ebu_lock, flags); } static int xway_dev_ready(struct mtd_info *mtd)