From patchwork Fri Sep 18 14:53:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 519331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 420461401F0 for ; Sat, 19 Sep 2015 00:57:31 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zcx4d-0000hR-FX; Fri, 18 Sep 2015 14:55:39 +0000 Received: from comal.ext.ti.com ([198.47.26.152]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Zcx4T-0000PB-5I; Fri, 18 Sep 2015 14:55:30 +0000 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id t8IEtAPd001219; Fri, 18 Sep 2015 09:55:10 -0500 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8IEtAsw008934; Fri, 18 Sep 2015 09:55:10 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Fri, 18 Sep 2015 09:55:09 -0500 Received: from rockdesk.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id t8IEseAO002598; Fri, 18 Sep 2015 09:55:07 -0500 From: Roger Quadros To: Subject: [PATCH v3 08/27] memory: omap-gpmc: Add IRQ ops for GPMC-NAND interface Date: Fri, 18 Sep 2015 17:53:30 +0300 Message-ID: <1442588029-13769-9-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1442588029-13769-1-git-send-email-rogerq@ti.com> References: <1442588029-13769-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150918_075529_479551_A5FA5C9A X-CRM114-Status: UNSURE ( 7.93 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -6.9 (------) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-6.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3) [198.47.26.152 listed in wl.mailspike.net] -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/, high trust [198.47.26.152 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-omap@vger.kernel.org, nsekhar@ti.com, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, ezequiel@vanguardiasur.com.ar, javier@dowhile0.org, computersforpeace@gmail.com, dwmw2@infradead.org, fcooper@ti.com, Roger Quadros Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Provide functions to enable/disable NAND IRQs, get NAND event status and clear NAND events. The NAND events of interest are TERMCOUNT and FIFOEVENT. Signed-off-by: Roger Quadros --- drivers/memory/omap-gpmc.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++ include/linux/omap-gpmc.h | 4 ++++ 2 files changed, 54 insertions(+) diff --git a/drivers/memory/omap-gpmc.c b/drivers/memory/omap-gpmc.c index a9071bb..e75226d 100644 --- a/drivers/memory/omap-gpmc.c +++ b/drivers/memory/omap-gpmc.c @@ -1078,8 +1078,58 @@ static bool gpmc_nand_writebuffer_empty(void) return false; } +static int gpmc_nand_irq_enable(enum gpmc_nand_irq irq) +{ + u32 reg; + + if (irq > GPMC_NAND_IRQ_TERMCOUNT) + return -EINVAL; + + reg = gpmc_read_reg(GPMC_IRQENABLE); + reg |= BIT(irq); + gpmc_write_reg(GPMC_IRQENABLE, reg); + + return 0; +} + +static int gpmc_nand_irq_disable(enum gpmc_nand_irq irq) +{ + u32 reg; + + if (irq > GPMC_NAND_IRQ_TERMCOUNT) + return -EINVAL; + + reg = gpmc_read_reg(GPMC_IRQENABLE); + reg &= ~BIT(irq); + gpmc_write_reg(GPMC_IRQENABLE, reg); + + return 0; +} + +static void gpmc_nand_irq_clear(enum gpmc_nand_irq irq) +{ + if (irq > GPMC_NAND_IRQ_TERMCOUNT) + return; + + /* setting bit to 1 clears the bit in IRQSTATUS */ + gpmc_write_reg(GPMC_IRQSTATUS, BIT(irq)); +} + +static u32 gpmc_nand_irq_status(void) +{ + u32 reg = gpmc_read_reg(GPMC_IRQSTATUS); + + /* Mask out non-NAND bits */ + reg &= GPMC_IRQENABLE_FIFOEVENT | GPMC_IRQENABLE_TERMCOUNT; + return reg; +} + static struct gpmc_nand_ops nand_ops = { .nand_writebuffer_empty = gpmc_nand_writebuffer_empty, + .nand_irq_enable = gpmc_nand_irq_enable, + .nand_irq_disable = gpmc_nand_irq_disable, + .nand_irq_clear = gpmc_nand_irq_clear, + .nand_irq_status = gpmc_nand_irq_status, }; /** diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h index 58f6bd2..b76cec3 100644 --- a/include/linux/omap-gpmc.h +++ b/include/linux/omap-gpmc.h @@ -11,6 +11,10 @@ #define GPMC_CONFIG_WP 0x00000005 +/* GPMC IRQENABLE/IRQSTATUS BIT defs */ +#define GPMC_IRQENABLE_FIFOEVENT BIT(0) +#define GPMC_IRQENABLE_TERMCOUNT BIT(1) + enum gpmc_nand_irq { GPMC_NAND_IRQ_FIFOEVENT = 0, GPMC_NAND_IRQ_TERMCOUNT,