From patchwork Wed Aug 19 22:40:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezequiel Garcia X-Patchwork-Id: 508856 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 8935B140771 for ; Thu, 20 Aug 2015 08:46:41 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZSC5r-0005rw-32; Wed, 19 Aug 2015 22:44:27 +0000 Received: from mail-qg0-f51.google.com ([209.85.192.51]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ZSC5n-0005qx-PB for linux-mtd@lists.infradead.org; Wed, 19 Aug 2015 22:44:25 +0000 Received: by qgj62 with SMTP id 62so16418523qgj.2 for ; Wed, 19 Aug 2015 15:44:02 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=8siSW9qt5lOSzbxXBRn7qkDq8Dhufr4EFRJY52ZdqW4=; b=E9EC3BctlLBps5+yhm4FAAmp1KCmIjF+ed236Pbmgr1d8LehVMy7acr7heGia6GNP/ IbiNDOQ5XPZIV+xMvwrDOF9W6CGKDO063aqT5TUalfkUnx5Q4/lwV1w1sQlE0pQLARyH GFzysPUzbCN2u+0IixRjOkyDM8Pa9qoPPEQqX0AS8rW7UDL1F+70YrrccDoI4ps7R2RZ sK9W85lYtXnxFUKFNNX4/rJQRKQYkEtZIu9DFE/oiOqaYo6VFg5rkHDNutLePN1du+Nw CyUHWFjegf5f8pnkfl9hG8FF3MzRam7W6RvQ39NMTyDKuLmnl4Q7A8iH2R04oqGMoeTj 1f1g== X-Gm-Message-State: ALoCoQkuMr89WJH8sfQvZ0vRf3cTXuBUz3cyqDKUE6sYXwighpUZMAlK1tI03kD6O/EYM8VLOSU7 X-Received: by 10.140.99.107 with SMTP id p98mr27708090qge.39.1440024242398; Wed, 19 Aug 2015 15:44:02 -0700 (PDT) Received: from localhost.localdomain ([190.2.108.156]) by smtp.gmail.com with ESMTPSA id q45sm1207747qgq.0.2015.08.19.15.43.59 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 19 Aug 2015 15:44:00 -0700 (PDT) From: Ezequiel Garcia To: Brian Norris , robert.jarzmik@free.fr, Subject: [PATCH v2] nand: pxa3xx: Increase READ_ID buffer and make the size static Date: Wed, 19 Aug 2015 19:40:09 -0300 Message-Id: <1440024009-20177-1-git-send-email-ezequiel@vanguardiasur.com.ar> X-Mailer: git-send-email 2.4.6 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20150819_154423_894922_A93CA49E X-CRM114-Status: GOOD ( 15.17 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.192.51 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [209.85.192.51 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jogo@openwrt.org, Ezequiel Garcia MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The read ID count should be made as large as the maximum READ_ID size, so there's no need to have dynamic size. This commit sets the hardware maximum read ID count, which should be more than enough on all cases. Also, we get rid of the read_id_bytes, and use a macro instead. Signed-off-by: Ezequiel Garcia --- Changes from v1: * Keep "data_size" to 8 bytes, as per hardware requirements to read at least a FIFO entry. * While here, add a proper comment on READ_ID_BYTES' definition. drivers/mtd/nand/pxa3xx_nand.c | 31 ++++++++++--------------------- 1 file changed, 10 insertions(+), 21 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 51f8a58..740983a 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -129,6 +129,13 @@ #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */ #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */ +/* + * This should be large enough to read 'ONFI' and 'JEDEC'. + * Let's use 7 bytes, which is the maximum ID count supported + * by the controller (see NDCR_RD_ID_CNT_MASK). + */ +#define READ_ID_BYTES 7 + /* macros for registers read/write */ #define nand_writel(info, off, val) \ writel_relaxed((val), (info)->mmio_base + (off)) @@ -176,8 +183,6 @@ struct pxa3xx_nand_host { /* calculated from pxa3xx_nand_flash data */ unsigned int col_addr_cycles; unsigned int row_addr_cycles; - size_t read_id_bytes; - }; struct pxa3xx_nand_info { @@ -917,7 +922,7 @@ static int prepare_set_command(struct pxa3xx_nand_info *info, int command, break; case NAND_CMD_READID: - info->buf_count = host->read_id_bytes; + info->buf_count = READ_ID_BYTES; info->ndcb0 |= NDCB0_CMD_TYPE(3) | NDCB0_ADDR_CYC(1) | command; @@ -1254,9 +1259,6 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, return -EINVAL; } - /* calculate flash information */ - host->read_id_bytes = (f->page_size == 2048) ? 4 : 2; - /* calculate addressing information */ host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1; @@ -1272,7 +1274,7 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0; ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; - ndcr |= NDCR_RD_ID_CNT(host->read_id_bytes); + ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); ndcr |= NDCR_SPARE_EN; /* enable spare by default */ info->reg_ndcr = ndcr; @@ -1283,23 +1285,10 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info, static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) { - /* - * We set 0 by hard coding here, for we don't support keep_config - * when there is more than one chip attached to the controller - */ - struct pxa3xx_nand_host *host = info->host[0]; uint32_t ndcr = nand_readl(info, NDCR); - if (ndcr & NDCR_PAGE_SZ) { - /* Controller's FIFO size */ - info->chunk_size = 2048; - host->read_id_bytes = 4; - } else { - info->chunk_size = 512; - host->read_id_bytes = 2; - } - /* Set an initial chunk size */ + info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; info->reg_ndcr = ndcr & ~NDCR_INT_MASK; info->ndtr0cs0 = nand_readl(info, NDTR0CS0); info->ndtr1cs0 = nand_readl(info, NDTR1CS0);