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[3/5,v4] mtd: spi-nor: fsl-quadspi: Enable support big endian registers

Message ID 1435656518-14022-3-git-send-email-haikun.wang@freescale.com
State Superseded
Headers show

Commit Message

Haikun.Wang@freescale.com June 30, 2015, 9:28 a.m. UTC 
QSPI registers are big endian on LS1021A.
This patch check endianness before accessing register and
swap the data if QSPI register is big endian.

Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
---
Changes in v4:
- Split into three patches

Changes in v3:
- Rebase with l2-mtd.git

Changes in v2:
- Fix compile issue

 drivers/mtd/spi-nor/fsl-quadspi.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
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Patch

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index d65e073..e416b08 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -260,12 +260,14 @@  static inline int is_imx6sx_qspi(struct fsl_qspi *q)
 
 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
 {
-	writel(val, addr);
+	q->devtype_data->driver_data & QUADSPI_QUIRK_REGMAP_BE ?
+		writel(cpu_to_be32(val), addr) : writel(val, addr);
 }
 
 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
 {
-	return	readl(addr);
+	return q->devtype_data->driver_data & QUADSPI_QUIRK_REGMAP_BE ?
+		cpu_to_be32(readl(addr)) : readl(addr);
 }