From patchwork Wed Apr 23 10:16:54 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 341805 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 21C3414008E for ; Wed, 23 Apr 2014 21:48:13 +1000 (EST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1WcvdY-0001Ny-9T; Wed, 23 Apr 2014 11:46:48 +0000 Received: from merlin.infradead.org ([2001:4978:20e::2]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1WcvdR-0001Jp-Vu; Wed, 23 Apr 2014 11:46:42 +0000 Received: from mail-by2ln0169.outbound.protection.outlook.com ([2a01:111:f400:7c0c::169] helo=na01-by2-obe.outbound.protection.outlook.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1Wcv8X-0004Z4-JG; Wed, 23 Apr 2014 11:14:52 +0000 Received: from CH1PR03CA011.namprd03.prod.outlook.com (10.255.156.156) by BL2PR03MB419.namprd03.prod.outlook.com (10.141.92.18) with Microsoft SMTP Server (TLS) id 15.0.921.12; Wed, 23 Apr 2014 11:14:22 +0000 Received: from BL2FFO11FD031.protection.gbl (10.255.156.132) by CH1PR03CA011.outlook.office365.com (10.255.156.156) with Microsoft SMTP Server (TLS) id 15.0.929.12 via Frontend Transport; Wed, 23 Apr 2014 11:14:21 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BL2FFO11FD031.mail.protection.outlook.com (10.173.160.71) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Wed, 23 Apr 2014 11:14:21 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3NBDxmZ008408; Wed, 23 Apr 2014 04:14:18 -0700 From: Huang Shijie To: Subject: [PATCH v1 6/7] mtd: fsl-quadspi: use the information stored in spi-nor{} Date: Wed, 23 Apr 2014 18:16:54 +0800 Message-ID: <1398248215-26768-7-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.2.rc3 In-Reply-To: References: X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(189002)(199002)(377424004)(77096999)(47776003)(79102001)(80022001)(77982001)(20776003)(93916002)(50986999)(76176999)(81342001)(80976001)(99396002)(19580405001)(83322001)(19580395003)(87936001)(89996001)(11926002)(88136002)(31966008)(6806004)(44976005)(48376002)(46102001)(92566001)(76482001)(92726001)(50466002)(4396001)(50226001)(77156001)(36756003)(74662001)(74502001)(62966002)(85852003)(83072002)(87286001)(81542001)(33646001)(42262001); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2PR03MB419; H:az84smr01.freescale.net; FPR:B03E2453.AC3C2815.5DFAD170.487A96B3.2029D; MLV:sfv; PTR:gate-az5.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01901B3451 Received-SPF: None (: freescale.com does not designate permitted sender hosts) X-OriginatorOrg: freescale.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20140423_071448_339938_4EABD5F6 X-CRM114-Status: GOOD ( 11.83 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: marex@denx.de, devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-spi@vger.kernel.org, Huang Shijie , linux-mtd@lists.infradead.org, computersforpeace@gmail.com, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org We can get the read/write/erase opcode from the spi nor framework now. What's more is that we can get the correct dummy cycles. This patch uses the information stored in the spi_nor{} to remove the hardcode in the fsl_qspi_init_lut(). Signed-off-by: Huang Shijie --- drivers/mtd/spi-nor/fsl-quadspi.c | 57 ++++++++++++------------------------ 1 files changed, 19 insertions(+), 38 deletions(-) diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 15bdeb9..0a2901e 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -280,8 +280,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) { void __iomem *base = q->iobase; int rxfifo = q->devtype_data->rxfifo; + struct spi_nor *nor = &q->nor[0]; + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; u32 lut_base; - u8 cmd, addrlen, dummy; + u8 op, dm; int i; fsl_qspi_unlock_lut(q); @@ -292,40 +294,29 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Quad Read */ lut_base = SEQID_QUAD_READ * 4; - - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_READ_1_1_4; - addrlen = ADDR24BIT; - dummy = 8; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_READ_1_1_4; - addrlen = ADDR32BIT; - dummy = 8; + op = nor->read_opcode; + dm = nor->read_dummy; + if (nor->flash_read == SPI_NOR_QUAD) { + if (op == SPINOR_OP_READ_1_1_4 || op == SPINOR_OP_READ4_1_1_4) { + /* read mode : 1-1-4 */ + writel(LUT0(CMD, PAD1, op) | LUT1(ADDR, PAD1, addrlen), + base + QUADSPI_LUT(lut_base)); + + writel(LUT0(DUMMY, PAD1, dm) | LUT1(READ, PAD4, rxfifo), + base + QUADSPI_LUT(lut_base + 1)); + } else { + dev_err(nor->dev, + "Unsupported cmd:%.2x\n", nor->read_opcode); + } } - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), - base + QUADSPI_LUT(lut_base)); - writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo), - base + QUADSPI_LUT(lut_base + 1)); - /* Write enable */ lut_base = SEQID_WREN * 4; writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); /* Page Program */ lut_base = SEQID_PP * 4; - - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_PP; - addrlen = ADDR24BIT; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_PP; - addrlen = ADDR32BIT; - } - - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + writel(LUT0(CMD, PAD1, nor->program_opcode) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); @@ -336,17 +327,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) /* Erase a sector */ lut_base = SEQID_SE * 4; - - if (q->nor_size <= SZ_16M) { - cmd = SPINOR_OP_SE; - addrlen = ADDR24BIT; - } else { - /* use the 4-byte address */ - cmd = SPINOR_OP_SE; - addrlen = ADDR32BIT; - } - - writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), + writel(LUT0(CMD, PAD1, nor->erase_opcode) | LUT1(ADDR, PAD1, addrlen), base + QUADSPI_LUT(lut_base)); /* Erase the whole chip */