From patchwork Mon Aug 19 04:10:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huang Shijie X-Patchwork-Id: 268077 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 844832C015E for ; Mon, 19 Aug 2013 14:14:34 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VBGrC-0002mB-DE; Mon, 19 Aug 2013 04:14:18 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1VBGr5-0002yB-Rj; Mon, 19 Aug 2013 04:14:12 +0000 Received: from co9ehsobe003.messaging.microsoft.com ([207.46.163.26] helo=co9outboundpool.messaging.microsoft.com) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1VBGqn-0002tT-SI; Mon, 19 Aug 2013 04:13:58 +0000 Received: from mail164-co9-R.bigfish.com (10.236.132.237) by CO9EHSOBE026.bigfish.com (10.236.130.89) with Microsoft SMTP Server id 14.1.225.22; Mon, 19 Aug 2013 04:13:32 +0000 Received: from mail164-co9 (localhost [127.0.0.1]) by mail164-co9-R.bigfish.com (Postfix) with ESMTP id 3489C1E0170; Mon, 19 Aug 2013 04:13:32 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zzzz1f42h208ch1ee6h1de0h1fdah2073h1202h1e76h1d1ah1d2ah1fc6h1082kzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h1155h) Received: from mail164-co9 (localhost.localdomain [127.0.0.1]) by mail164-co9 (MessageSwitch) id 1376885611224194_9319; Mon, 19 Aug 2013 04:13:31 +0000 (UTC) Received: from CO9EHSMHS032.bigfish.com (unknown [10.236.132.236]) by mail164-co9.bigfish.com (Postfix) with ESMTP id 3030610004D; Mon, 19 Aug 2013 04:13:31 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by CO9EHSMHS032.bigfish.com (10.236.130.42) with Microsoft SMTP Server (TLS) id 14.16.227.3; Mon, 19 Aug 2013 04:13:31 +0000 Received: from tx30smr01.am.freescale.net (10.81.153.31) by 039-SN1MMR1-005.039d.mgd.msft.net (10.84.1.17) with Microsoft SMTP Server (TLS) id 14.3.146.2; Mon, 19 Aug 2013 04:13:30 +0000 Received: from shlinux2.ap.freescale.net (shlinux2.ap.freescale.net [10.192.224.44]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id r7J4DDUS002618; Sun, 18 Aug 2013 21:13:26 -0700 From: Huang Shijie To: Subject: [PATCH V1 3/5] mtd: m25p80: add the quad-read support Date: Mon, 19 Aug 2013 12:10:01 +0800 Message-ID: <1376885403-12156-4-git-send-email-b32955@freescale.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1376885403-12156-1-git-send-email-b32955@freescale.com> References: <1376885403-12156-1-git-send-email-b32955@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130819_001354_197647_F41A8814 X-CRM114-Status: GOOD ( 19.90 ) X-Spam-Score: -4.2 (----) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-4.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/, medium trust [207.46.163.26 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: shawn.guo@linaro.org, b44548@freescale.com, dedekind1@gmail.com, b18965@freescale.com, linux-spi@vger.kernel.org, Huang Shijie , linux-mtd@lists.infradead.org, kernel@pengutronix.de, computersforpeace@gmail.com, dwmw2@infradead.org, linux-arm-kernel@lists.infradead.org X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This patch adds the quad read support: (1) Add the relative commands: OPCODE_QIOR, OPCODE_4QIOR, OPCODE_RDCR, also add the relative macro for the Configuartion Register. (2) add the "m25p,quad-read" property for the m25p80 driver If the dts has the "m25p,quad-read" property, the kernel will set the Quad bit of the configuration register, and when the setting is suceeded, we set the read opcode with OPCODE_QIOR. Signed-off-by: Huang Shijie --- Documentation/devicetree/bindings/mtd/m25p80.txt | 5 ++ drivers/mtd/devices/m25p80.c | 51 ++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 6 +++ 3 files changed, 62 insertions(+), 0 deletions(-) diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/m25p80.txt index 6d3d576..b33313f 100644 --- a/Documentation/devicetree/bindings/mtd/m25p80.txt +++ b/Documentation/devicetree/bindings/mtd/m25p80.txt @@ -17,6 +17,11 @@ Optional properties: Refer to your chips' datasheet to check if this is supported by your chip. +- m25p,quad-read : Use the "quad read" opcode to read data from the chip instead + of the usual "read" opcode. This opcode is not supported by + all chips and support for it can not be detected at runtime. + Refer to your chips' datasheet to check if this is supported + by your chip. Example: flash: m25p80@0 { diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c index f3598c1..4bc9b1b 100644 --- a/drivers/mtd/devices/m25p80.c +++ b/drivers/mtd/devices/m25p80.c @@ -103,6 +103,40 @@ static int write_sr(struct m25p *flash, u8 val) } /* + * Read the configuration register, returning its value in the location + * Return the configuration register value. + * Returns negative if error occurred. + */ +static int read_cr(struct m25p *flash) +{ + u8 code = OPCODE_RDCR; + int ret; + u8 val; + + ret = spi_write_then_read(flash->spi, &code, 1, &val, 1); + if (ret < 0) { + dev_err(&flash->spi->dev, "error %d reading CR\n", ret); + return ret; + } + return val; +} + +/* + * Write status register and configuration register with 2 bytes + * The first byte will be written to the status register, while the second byte + * will be written to the configuration register. + * Returns negative if error occurred. + */ +static int write_sr_cr(struct m25p *flash, u16 val) +{ + flash->command[0] = OPCODE_WRSR; + flash->command[1] = 0; + flash->command[2] = (val >> 8); + + return spi_write(flash->spi, flash->command, 3); +} + +/* * Set write enable latch with Write Enable command. * Returns negative if error occurred. */ @@ -880,6 +914,8 @@ static int m25p_probe(struct spi_device *spi) unsigned i; struct mtd_part_parser_data ppdata; struct device_node __maybe_unused *np = spi->dev.of_node; + u16 sr_cr; + int ret; #ifdef CONFIG_MTD_OF_PARTS if (!of_device_is_available(np)) @@ -1014,6 +1050,21 @@ static int m25p_probe(struct spi_device *spi) else flash->read_opcode = OPCODE_NORM_READ; + /* Try to enable the Quad Read */ + if (np && of_property_read_bool(np, "m25p,quad-read")) { + /* The configuration register is set by the second byte. */ + sr_cr = CR_QUAD << 8; + + /* Write the QUAD bit to the Configuration Register. */ + write_enable(flash); + if (write_sr_cr(flash, sr_cr) == 0) { + /* read back and check it */ + ret = read_cr(flash); + if (ret > 0 && (ret & CR_QUAD)) + flash->read_opcode = OPCODE_QIOR; + } + } + flash->program_opcode = OPCODE_PP; if (info->addr_width) diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b420a5b..d5b189d 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -39,6 +39,9 @@ /* Used for Spansion flashes only. */ #define OPCODE_BRWR 0x17 /* Bank register write */ +#define OPCODE_QIOR 0xeb /* Quad read */ +#define OPCODE_4QIOR 0xec /* Quad read */ +#define OPCODE_RDCR 0x35 /* Read configuration register */ /* Status Register bits. */ #define SR_WIP 1 /* Write in progress */ @@ -49,4 +52,7 @@ #define SR_BP2 0x10 /* Block protect 2 */ #define SR_SRWD 0x80 /* SR write protect */ +/* Configuration Register bits. */ +#define CR_QUAD 0x2 /* Quad I/O */ + #endif /* __LINUX_MTD_SPI_NOR_H */