From patchwork Mon Jul 29 10:53:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?546L5a6H6Iiq?= X-Patchwork-Id: 262715 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from casper.infradead.org (unknown [IPv6:2001:770:15f::2]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7F0BE2C0108 for ; Mon, 29 Jul 2013 20:55:02 +1000 (EST) Received: from merlin.infradead.org ([2001:4978:20e::2]) by casper.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3l6L-0003st-Ay; Mon, 29 Jul 2013 10:54:53 +0000 Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3l6J-00030q-Dj; Mon, 29 Jul 2013 10:54:51 +0000 Received: from mail-pb0-x235.google.com ([2607:f8b0:400e:c01::235]) by merlin.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1V3l6G-0002zI-2B for linux-mtd@lists.infradead.org; Mon, 29 Jul 2013 10:54:49 +0000 Received: by mail-pb0-f53.google.com with SMTP id up15so3855015pbc.12 for ; Mon, 29 Jul 2013 03:54:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=LxIa6Lnvhki9xavvv/0VwKLrtIZPDU/GXJVm96DyXjM=; b=jaoPJ0lYqz3uJDhmcm2eXv9u+hGHMgZ6We2nN0ckDbns7XFQNWQiueRLAh90GbJS3L ym5+CAk+/hfmJ2JKca/Uc4e/y5XTWyhZdC+pZjI4LWTecUB/lieP2BEyTIr3PfYFXtdv U4rgbLS+RsBrlD+hOZYXzSyPERgD2H0+ppPhNcdToMetM6kZNe+ugE6Cy1dOIAqAMaNA 1/NCHCySST/sXsmp32ok5CLXtB82p1N7nUi263GrZ2/qrwkeqNqt8cTgYbmxHxVU65d8 7D4rMOeEzfViG3yjRJmhIPe9VYFZFcEHyxtWbVyzWWnwiB9LRmkUstgF5oANpvCMWyZZ 2haw== X-Received: by 10.66.2.130 with SMTP id 2mr68069145pau.13.1375095266230; Mon, 29 Jul 2013 03:54:26 -0700 (PDT) Received: from localhost.localdomain ([218.24.172.134]) by mx.google.com with ESMTPSA id ep4sm76256454pbd.35.2013.07.29.03.54.23 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 29 Jul 2013 03:54:25 -0700 (PDT) From: wangyuhang To: broonie@kernel.org Subject: [PATCH] SPI: DUAL and QUAD support Date: Mon, 29 Jul 2013 18:53:14 +0800 Message-Id: <1375095194-7093-1-git-send-email-wangyuhang2014@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <20130729064234.GS9858@sirena.org.uk> References: <20130729064234.GS9858@sirena.org.uk> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20130729_065448_295055_B4668664 X-CRM114-Status: GOOD ( 21.35 ) X-Spam-Score: -1.8 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail provider (wangyuhang2014[at]gmail.com) -0.0 SPF_PASS SPF: sender matches SPF record 0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends in digit (wangyuhang2014[at]gmail.com) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature Cc: linux-mtd@lists.infradead.org, pekon@ti.com, spi-devel-general@lists.sourceforge.net, sourav.poddar@ti.com, tpiepho@gmail.com, wangyuhang X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Hi, modify two things. 1: >> @@ -1316,6 +1324,12 @@ int spi_setup(struct spi_device *spi) >> /* help drivers fail *cleanly* when they need options >> * that aren't supported with their current master >> */ >> + if (((spi->mode >> 8) & 0x03) == 0x03 || >> + ((spi->mode >> 10) & 0x03) == 0x03) { >> + dev_err(&spi->dev, >> + "setup: can not select dual and quad at the same time\n") >> + return -EINVAL; >> + } >> + return -EINVAL; >> + } >This code won't work if the constants you added for mode flags change >value. More importantly, anyone searching the code for SPI_TX_DUAL, >etc. won't find this code. so use the certain macro to replace. 2: >You need to make sure that existing userspace binaries can run >unmodified, changing the types will change the layout of the ioctl >arguments. This may mean that you need to add new ioctls if you need to >change types. I recovered the SPI_IOC_RD_LSB_FIRST ioctl. Add new ioctl to fit u16 mode. In addition,may SPI_IOC_RD_LSB_FIRST should be del in a better way. Signed-off-by: wangyuhang --- drivers/spi/spi.c | 14 ++++++++++++++ drivers/spi/spidev.c | 29 ++++++++++++++++++++++++++++- include/linux/spi/spi.h | 20 ++++++++++++++++++-- include/uapi/linux/spi/spidev.h | 17 ++++++++++++++++- 4 files changed, 76 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index 004b10f..3f6dc93 100644 --- a/drivers/spi/spi.c +++ b/drivers/spi/spi.c @@ -868,6 +868,14 @@ static void of_register_spi_devices(struct spi_master *master) spi->mode |= SPI_CS_HIGH; if (of_find_property(nc, "spi-3wire", NULL)) spi->mode |= SPI_3WIRE; + if (of_find_property(nc, "spi-tx-dual", NULL)) + spi->mode |= SPI_TX_DUAL; + if (of_find_property(nc, "spi-tx-quad", NULL)) + spi->mode |= SPI_TX_QUAD; + if (of_find_property(nc, "spi-rx-dual", NULL)) + spi->mode |= SPI_RX_DUAL; + if (of_find_property(nc, "spi-rx-quad", NULL)) + spi->mode |= SPI_RX_QUAD; /* Device speed */ prop = of_get_property(nc, "spi-max-frequency", &len); @@ -1316,6 +1324,12 @@ int spi_setup(struct spi_device *spi) /* help drivers fail *cleanly* when they need options * that aren't supported with their current master */ + if (((spi->mode & SPI_TX_DUAL) && (spi->mode & SPI_TX_QUAD)) || + ((spi->mode & SPI_RX_DUAL) && (spi->mode & SPI_RX_QUAD))) { + dev_err(&spi->dev, + "setup: can not select dual and quad at the same time\n"); + return -EINVAL; + } bad_bits = spi->mode & ~spi->master->mode_bits; if (bad_bits) { dev_err(&spi->dev, "setup: unsupported mode bits %x\n", diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index 2e0655d..0b776de 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -75,6 +75,9 @@ static DECLARE_BITMAP(minors, N_SPI_MINORS); | SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \ | SPI_NO_CS | SPI_READY) +#define SPI_EXTMODE_MASK (SPI_MODE_MASK | SPI_TX_DUAL \ + | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD) + struct spidev_data { dev_t devt; spinlock_t spi_lock; @@ -268,6 +271,8 @@ static int spidev_message(struct spidev_data *spidev, k_tmp->bits_per_word = u_tmp->bits_per_word; k_tmp->delay_usecs = u_tmp->delay_usecs; k_tmp->speed_hz = u_tmp->speed_hz; + k_tmp->tx_nbits = u_tmp->tx_nbits; + k_tmp->rx_nbits = u_tmp->rx_nbits; #ifdef VERBOSE dev_dbg(&spidev->spi->dev, " xfer len %zd %s%s%s%dbits %u usec %uHz\n", @@ -369,7 +374,10 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) case SPI_IOC_RD_MAX_SPEED_HZ: retval = __put_user(spi->max_speed_hz, (__u32 __user *)arg); break; - + case SPI_IOC_EXTRD_MODE: + retval = __put_user(spi->mode & SPI_EXTMODE_MASK, + (__u16 __user *)arg); + break; /* write requests */ case SPI_IOC_WR_MODE: retval = __get_user(tmp, (u8 __user *)arg); @@ -433,6 +441,25 @@ spidev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) dev_dbg(&spi->dev, "%d Hz (max)\n", tmp); } break; + case SPI_IOC_EXTWR_MODE: + retval = __get_user(tmp, (u16 __user *)arg); + if (retval == 0) { + u16 save = spi->mode; + + if (tmp & ~SPI_EXTMODE_MASK) { + retval = -EINVAL; + break; + } + + tmp |= spi->mode & ~SPI_EXTMODE_MASK; + spi->mode = (u16)tmp; + retval = spi_setup(spi); + if (retval < 0) + spi->mode = save; + else + dev_dbg(&spi->dev, "spi mode %02x\n", tmp); + } + break; default: /* segmented and/or full-duplex I/O request */ diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index 38c2b92..222e49e 100644 --- a/include/linux/spi/spi.h +++ b/include/linux/spi/spi.h @@ -74,7 +74,7 @@ struct spi_device { struct spi_master *master; u32 max_speed_hz; u8 chip_select; - u8 mode; + u16 mode; #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ #define SPI_MODE_0 (0|0) /* (original MicroWire) */ @@ -87,6 +87,10 @@ struct spi_device { #define SPI_LOOP 0x20 /* loopback mode */ #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */ #define SPI_READY 0x80 /* slave pulls low to pause */ +#define SPI_TX_DUAL 0x100 /* transmit with 2 wires */ +#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */ +#define SPI_RX_DUAL 0x400 /* receive with 2 wires */ +#define SPI_RX_QUAD 0x800 /* receive with 4 wires */ u8 bits_per_word; int irq; void *controller_state; @@ -437,6 +441,8 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum); * @rx_buf: data to be read (dma-safe memory), or NULL * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped + * @tx_nbits: number of bits used for writting + * @rx_nbits: number of bits used for reading * @len: size of rx and tx buffers (in bytes) * @speed_hz: Select a speed other than the device default for this * transfer. If 0 the default (from @spi_device) is used. @@ -491,6 +497,11 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum); * by the results of previous messages and where the whole transaction * ends when the chipselect goes intactive. * + * When SPI can transfer in 1x,2x or 4x. It can get this tranfer information + * from device through @tx_nbits and @rx_nbits. In Bi-direction, these + * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x) + * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer. + * * The code that submits an spi_message (and its spi_transfers) * to the lower layers is responsible for managing its memory. * Zero-initialize every field you don't set up explicitly, to @@ -511,6 +522,11 @@ struct spi_transfer { dma_addr_t rx_dma; unsigned cs_change:1; + u8 tx_nbits; + u8 rx_nbits; +#define SPI_NBITS_SINGLE 0x0; /* 1bit transfer */ +#define SPI_NBITS_DUAL 0x01; /* 2bits transfer */ +#define SPI_NBITS_QUAD 0x02; /* 4bits transfer */ u8 bits_per_word; u16 delay_usecs; u32 speed_hz; @@ -858,7 +874,7 @@ struct spi_board_info { /* mode becomes spi_device.mode, and is essential for chips * where the default of SPI_CS_HIGH = 0 is wrong. */ - u8 mode; + u16 mode; /* ... may need additional spi_device chip config data here. * avoid stuff protocol drivers can set; but include stuff diff --git a/include/uapi/linux/spi/spidev.h b/include/uapi/linux/spi/spidev.h index 52d9ed0..4d47e8a 100644 --- a/include/uapi/linux/spi/spidev.h +++ b/include/uapi/linux/spi/spidev.h @@ -42,7 +42,14 @@ #define SPI_LOOP 0x20 #define SPI_NO_CS 0x40 #define SPI_READY 0x80 - +#define SPI_TX_DUAL 0x100 +#define SPI_TX_QUAD 0x200 +#define SPI_RX_DUAL 0x400 +#define SPI_RX_QUAD 0x800 + +#define SPI_NBITS_SINGLE 0x0; /* 1bit transfer */ +#define SPI_NBITS_DUAL 0x01; /* 2bits transfer */ +#define SPI_NBITS_QUAD 0x02; /* 4bits transfer */ /*---------------------------------------------------------------------------*/ /* IOCTL commands */ @@ -54,6 +61,8 @@ * @tx_buf: Holds pointer to userspace buffer with transmit data, or null. * If no data is provided, zeroes are shifted out. * @rx_buf: Holds pointer to userspace buffer for receive data, or null. + * @tx_nbits: number of bits used for writting. + * @rx_nbits: number of bits used for reading. * @len: Length of tx and rx buffers, in bytes. * @speed_hz: Temporary override of the device's bitrate. * @bits_per_word: Temporary override of the device's wordsize. @@ -85,6 +94,8 @@ struct spi_ioc_transfer { __u64 tx_buf; __u64 rx_buf; + __u8 tx_nbits; + __u8 rx_nbits; __u32 len; __u32 speed_hz; @@ -126,6 +137,10 @@ struct spi_ioc_transfer { #define SPI_IOC_RD_MAX_SPEED_HZ _IOR(SPI_IOC_MAGIC, 4, __u32) #define SPI_IOC_WR_MAX_SPEED_HZ _IOW(SPI_IOC_MAGIC, 4, __u32) +/* Read / Write of SPI mode (including SPI DUAL/QUAD) */ +#define SPI_IOC_EXTRD_MODE _IOR(SPI_IOC_MAGIC, 5, __u16) +#define SPI_IOC_EXTWR_MODE _IOW(SPI_IOC_MAGIC, 5, __u16) + #endif /* SPIDEV_H */